[PATCH v3 2/6] firmware: qcom_scm: Add gpu_init_regs call

[Bjorn Andersson]

On Tue, Apr 30, 2024 at 11:43:16AM GMT, Connor Abbott wrote:
> This will used by drm/msm to initialize GPU registers that Qualcomm's
> firmware doesn't make writeable to the kernel.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> Signed-off-by: Connor Abbott <cwabbott0 at gmail.com>

Acked-by: Bjorn Andersson <andersson at kernel.org>

Regards,
Bjorn

> ---
>  drivers/firmware/qcom/qcom_scm.c       | 14 ++++++++++++++
>  drivers/firmware/qcom/qcom_scm.h       |  3 +++
>  include/linux/firmware/qcom/qcom_scm.h | 23 +++++++++++++++++++++++
>  3 files changed, 40 insertions(+)
> 
> diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
> index 06e46267161b..f8623ad0987c 100644
> --- a/drivers/firmware/qcom/qcom_scm.c
> +++ b/drivers/firmware/qcom/qcom_scm.c
> @@ -1394,6 +1394,20 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
>  }
>  EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh);
>  
> +int qcom_scm_gpu_init_regs(u32 gpu_req)
> +{
> +	struct qcom_scm_desc desc = {
> +		.svc = QCOM_SCM_SVC_GPU,
> +		.cmd = QCOM_SCM_SVC_GPU_INIT_REGS,
> +		.arginfo = QCOM_SCM_ARGS(1),
> +		.args[0] = gpu_req,
> +		.owner = ARM_SMCCC_OWNER_SIP,
> +	};
> +
> +	return qcom_scm_call(__scm->dev, &desc, NULL);
> +}
> +EXPORT_SYMBOL_GPL(qcom_scm_gpu_init_regs);
> +
>  static int qcom_scm_find_dload_address(struct device *dev, u64 *addr)
>  {
>  	struct device_node *tcsr;
> diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_scm.h
> index 4532907e8489..484e030bcac9 100644
> --- a/drivers/firmware/qcom/qcom_scm.h
> +++ b/drivers/firmware/qcom/qcom_scm.h
> @@ -138,6 +138,9 @@ int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
>  #define QCOM_SCM_WAITQ_RESUME			0x02
>  #define QCOM_SCM_WAITQ_GET_WQ_CTX		0x03
>  
> +#define QCOM_SCM_SVC_GPU			0x28
> +#define QCOM_SCM_SVC_GPU_INIT_REGS		0x01
> +
>  /* common error codes */
>  #define QCOM_SCM_V2_EBUSY	-12
>  #define QCOM_SCM_ENOMEM		-5
> diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h
> index aaa19f93ac43..a221a643dc12 100644
> --- a/include/linux/firmware/qcom/qcom_scm.h
> +++ b/include/linux/firmware/qcom/qcom_scm.h
> @@ -115,6 +115,29 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
>  int qcom_scm_lmh_profile_change(u32 profile_id);
>  bool qcom_scm_lmh_dcvsh_available(void);
>  
> +/*
> + * Request TZ to program set of access controlled registers necessary
> + * irrespective of any features
> + */
> +#define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0)
> +/*
> + * Request TZ to program BCL id to access controlled register when BCL is
> + * enabled
> + */
> +#define QCOM_SCM_GPU_BCL_EN_REQ BIT(1)
> +/*
> + * Request TZ to program set of access controlled register for CLX feature
> + * when enabled
> + */
> +#define QCOM_SCM_GPU_CLX_EN_REQ BIT(2)
> +/*
> + * Request TZ to program tsense ids to access controlled registers for reading
> + * gpu temperature sensors
> + */
> +#define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3)
> +
> +int qcom_scm_gpu_init_regs(u32 gpu_req);
> +
>  #ifdef CONFIG_QCOM_QSEECOM
>  
>  int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
> 
> -- 
> 2.31.1
>