[PATCH v15 11/13] drm/msm/dpu: support SSPP assignment for quad-pipe case
Jessica Zhang
jessica.zhang at oss.qualcomm.com
Wed Aug 20 18:17:21 UTC 2025
On 8/18/2025 6:31 PM, Jun Nie wrote:
> Currently, SSPPs are assigned to a maximum of two pipes. However,
> quad-pipe usage scenarios require four pipes and involve configuring
> two stages. In quad-pipe case, the first two pipes share a set of
> mixer configurations and enable multi-rect mode when certain
> conditions are met. The same applies to the subsequent two pipes.
>
> Assign SSPPs to the pipes in each stage using a unified method and
> to loop the stages accordingly.
>
> Signed-off-by: Jun Nie <jun.nie at linaro.org>
Reviewed-by: Jessica Zhang <jessica.zhang at oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 150 ++++++++++++++++++------------
> 1 file changed, 89 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index d3db843d324efcda5477a7eac73a8872a55e95e5..99c902dfa7e0256028d294113a3e9bad0e1a0069 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -957,6 +957,23 @@ static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *sspp,
> dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth);
> }
>
> +static bool dpu_plane_get_single_pipe_in_stage(struct dpu_plane_state *pstate,
> + struct dpu_sw_pipe **single_pipe,
> + struct dpu_sw_pipe_cfg **single_pipe_cfg,
> + int stage_index)
> +{
> + int pipe_idx;
> +
> + pipe_idx = stage_index * PIPES_PER_STAGE;
> + if (drm_rect_width(&pstate->pipe_cfg[pipe_idx].src_rect) != 0 &&
> + drm_rect_width(&pstate->pipe_cfg[pipe_idx + 1].src_rect) == 0) {
> + *single_pipe = &pstate->pipe[pipe_idx];
> + *single_pipe_cfg = &pstate->pipe_cfg[pipe_idx];
> + return true;
> + }
> +
> + return false;
> +}
>
> static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
> struct drm_atomic_state *state,
> @@ -1022,17 +1039,20 @@ static bool dpu_plane_try_multirect_parallel(struct dpu_sw_pipe *pipe, struct dp
> static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
> struct dpu_plane_state *prev_adjacent_pstate,
> const struct msm_format *fmt,
> - uint32_t max_linewidth)
> + uint32_t max_linewidth, int stage_index)
> {
> - struct dpu_sw_pipe *pipe = &pstate->pipe[0];
> - struct dpu_sw_pipe *r_pipe = &pstate->pipe[1];
> - struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg[0];
> - struct dpu_sw_pipe *prev_pipe = &prev_adjacent_pstate->pipe[0];
> - struct dpu_sw_pipe_cfg *prev_pipe_cfg = &prev_adjacent_pstate->pipe_cfg[0];
> + struct dpu_sw_pipe *pipe, *prev_pipe;
> + struct dpu_sw_pipe_cfg *pipe_cfg, *prev_pipe_cfg;
> const struct msm_format *prev_fmt = msm_framebuffer_format(prev_adjacent_pstate->base.fb);
> u16 max_tile_height = 1;
>
> - if (prev_adjacent_pstate->pipe[1].sspp != NULL ||
> + if (!dpu_plane_get_single_pipe_in_stage(pstate, &pipe,
> + &pipe_cfg, stage_index))
> + return false;
> +
> + if (!dpu_plane_get_single_pipe_in_stage(prev_adjacent_pstate,
> + &prev_pipe, &prev_pipe_cfg,
> + stage_index) ||
> prev_pipe->multirect_mode != DPU_SSPP_MULTIRECT_NONE)
> return false;
>
> @@ -1047,11 +1067,6 @@ static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate,
> if (MSM_FORMAT_IS_UBWC(prev_fmt))
> max_tile_height = max(max_tile_height, prev_fmt->tile_height);
>
> - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> -
> - r_pipe->sspp = NULL;
> -
> if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) &&
> dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth) &&
> (pipe_cfg->dst_rect.x1 >= prev_pipe_cfg->dst_rect.x2 ||
> @@ -1180,36 +1195,69 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
> return 0;
> }
>
> +static int dpu_plane_assign_resource_in_stage(struct dpu_sw_pipe *pipe,
> + struct dpu_sw_pipe_cfg *pipe_cfg,
> + struct drm_plane_state *plane_state,
> + struct dpu_global_state *global_state,
> + struct drm_crtc *crtc,
> + struct dpu_rm_sspp_requirements *reqs)
> +{
> + struct drm_plane *plane = plane_state->plane;
> + struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> + struct dpu_sw_pipe *r_pipe = pipe + 1;
> + struct dpu_sw_pipe_cfg *r_pipe_cfg = pipe_cfg + 1;
> +
> + if (drm_rect_width(&pipe_cfg->src_rect) == 0)
> + return 0;
> +
> + pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs);
> + if (!pipe->sspp)
> + return -ENODEV;
> + pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> +
> + if (drm_rect_width(&r_pipe_cfg->src_rect) == 0)
> + return 0;
> +
> + if (dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
> + pipe->sspp,
> + msm_framebuffer_format(plane_state->fb),
> + dpu_kms->catalog->caps->max_linewidth))
> + return 0;
> +
> + r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs);
> + if (!r_pipe->sspp)
> + return -ENODEV;
> + r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> + r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> +
> + return 0;
> +}
> +
> static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> struct dpu_global_state *global_state,
> struct drm_atomic_state *state,
> struct drm_plane_state *plane_state,
> - struct drm_plane_state *prev_adjacent_plane_state)
> + struct drm_plane_state **prev_adjacent_plane_state)
> {
> const struct drm_crtc_state *crtc_state = NULL;
> struct drm_plane *plane = plane_state->plane;
> struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
> struct dpu_rm_sspp_requirements reqs;
> - struct dpu_plane_state *pstate, *prev_adjacent_pstate;
> + struct dpu_plane_state *pstate, *prev_adjacent_pstate[STAGES_PER_PLANE];
> struct dpu_sw_pipe *pipe;
> - struct dpu_sw_pipe *r_pipe;
> struct dpu_sw_pipe_cfg *pipe_cfg;
> - struct dpu_sw_pipe_cfg *r_pipe_cfg;
> const struct msm_format *fmt;
> - int i;
> + int i, ret;
>
> if (plane_state->crtc)
> crtc_state = drm_atomic_get_new_crtc_state(state,
> plane_state->crtc);
>
> pstate = to_dpu_plane_state(plane_state);
> - prev_adjacent_pstate = prev_adjacent_plane_state ?
> - to_dpu_plane_state(prev_adjacent_plane_state) : NULL;
> -
> - pipe = &pstate->pipe[0];
> - r_pipe = &pstate->pipe[1];
> - pipe_cfg = &pstate->pipe_cfg[0];
> - r_pipe_cfg = &pstate->pipe_cfg[1];
> + for (i = 0; i < STAGES_PER_PLANE; i++)
> + prev_adjacent_pstate[i] = prev_adjacent_plane_state[i] ?
> + to_dpu_plane_state(prev_adjacent_plane_state[i]) : NULL;
>
> for (i = 0; i < PIPES_PER_PLANE; i++)
> pstate->pipe[i].sspp = NULL;
> @@ -1224,42 +1272,24 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
>
> reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);
>
> - if (drm_rect_width(&r_pipe_cfg->src_rect) == 0) {
> - if (!prev_adjacent_pstate ||
> - !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt,
> - dpu_kms->catalog->caps->max_linewidth)) {
> - pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> - if (!pipe->sspp)
> - return -ENODEV;
> -
> - r_pipe->sspp = NULL;
> + for (i = 0; i < STAGES_PER_PLANE; i++) {
> + if (prev_adjacent_pstate[i] &&
> + dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate[i], fmt,
> + dpu_kms->catalog->caps->max_linewidth,
> + i))
> + continue;
>
> - pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> + if (dpu_plane_get_single_pipe_in_stage(pstate, &pipe, &pipe_cfg, i))
> + prev_adjacent_plane_state[i] = plane_state;
>
> - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> - }
> - } else {
> - pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> - if (!pipe->sspp)
> - return -ENODEV;
> -
> - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
> - pipe->sspp,
> - msm_framebuffer_format(plane_state->fb),
> - dpu_kms->catalog->caps->max_linewidth)) {
> - /* multirect is not possible, use two SSPP blocks */
> - r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
> - if (!r_pipe->sspp)
> - return -ENODEV;
> -
> - pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> -
> - r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
> - r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
> - }
> + pipe = &pstate->pipe[i * PIPES_PER_STAGE];
> + pipe_cfg = &pstate->pipe_cfg[i * PIPES_PER_STAGE];
> + ret = dpu_plane_assign_resource_in_stage(pipe, pipe_cfg,
> + plane_state,
> + global_state,
> + crtc, &reqs);
> + if (ret)
> + return ret;
> }
>
> return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
> @@ -1272,7 +1302,7 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state,
> unsigned int num_planes)
> {
> unsigned int i;
> - struct drm_plane_state *prev_adjacent_plane_state = NULL;
> + struct drm_plane_state *prev_adjacent_plane_state[STAGES_PER_PLANE] = { NULL };
>
> for (i = 0; i < num_planes; i++) {
> struct drm_plane_state *plane_state = states[i];
> @@ -1286,8 +1316,6 @@ int dpu_assign_plane_resources(struct dpu_global_state *global_state,
> prev_adjacent_plane_state);
> if (ret)
> break;
> -
> - prev_adjacent_plane_state = plane_state;
> }
>
> return 0;
>
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