[PATCH v2 10/16] drm/msm/dpu: Add handling of LM_6 and LM_7 bits in pending flush mask

[Jessica Zhang]

On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
> MDSS/MDP v12 comes with new bits in flush registers (e.g.
> MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

Reviewed-by: Jessica Zhang <quic_jesszhan at quicinc.com>

> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 0021df38f8662683771abb2cef7794c3209e9413..9d4866509e97c262006e15cf3e02a2f1ca851784 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -254,6 +254,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx,
>   	case LM_5:
>   		ctx->pending_flush_mask |= BIT(20);
>   		break;
> +	case LM_6:
> +		ctx->pending_flush_mask |= BIT(21);
> +		break;
> +	case LM_7:
> +		ctx->pending_flush_mask |= BIT(27);
> +		break;
>   	default:
>   		break;
>   	}
> 
> -- 
> 2.43.0
>