[PATCH 1/5] drm/msm/a6xx: Fix gpucc register block for A621

[Akhil P Oommen]

On 2/18/2025 11:52 PM, Rob Clark wrote:
> On Thu, Feb 13, 2025 at 8:10 AM Akhil P Oommen <quic_akhilpo at quicinc.com> wrote:
>>
>> From: Jie Zhang <quic_jiezh at quicinc.com>
>>
>> Adreno 621 has a different memory map for GPUCC block. So update
>> a6xx_gpu_state code to dump the correct set of gpucc registers.
>>
>> Signed-off-by: Jie Zhang <quic_jiezh at quicinc.com>
>> Signed-off-by: Akhil P Oommen <quic_akhilpo at quicinc.com>
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 13 ++++++++++---
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 17 +++++++++++++++++
>>  2 files changed, 27 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
>> index 0fcae53c0b14..2c10474ccc95 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c
>> @@ -1214,12 +1214,12 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
>>         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
>>
>>         a6xx_state->gmu_registers = state_kcalloc(a6xx_state,
>> -               3, sizeof(*a6xx_state->gmu_registers));
>> +               4, sizeof(*a6xx_state->gmu_registers));
>>
>>         if (!a6xx_state->gmu_registers)
>>                 return;
>>
>> -       a6xx_state->nr_gmu_registers = 3;
>> +       a6xx_state->nr_gmu_registers = 4;
> 
> nit, this and splitting out a6xx_gpucc_reg from a6xx_gmu_cx_registers
> could probably be it's own commit

Ack. Will split this patch.

-Akhil

> 
> BR,
> -R
> 
>>
>>         /* Get the CX GMU registers from AHB */
>>         _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[0],
>> @@ -1227,6 +1227,13 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
>>         _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[1],
>>                 &a6xx_state->gmu_registers[1], true);
>>
>> +       if (adreno_is_a621(adreno_gpu))
>> +               _a6xx_get_gmu_registers(gpu, a6xx_state, &a621_gpucc_reg,
>> +                       &a6xx_state->gmu_registers[2], false);
>> +       else
>> +               _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg,
>> +                       &a6xx_state->gmu_registers[2], false);
>> +
>>         if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu))
>>                 return;
>>
>> @@ -1234,7 +1241,7 @@ static void a6xx_get_gmu_registers(struct msm_gpu *gpu,
>>         gpu_write(gpu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
>>
>>         _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gmu_reglist[2],
>> -               &a6xx_state->gmu_registers[2], false);
>> +               &a6xx_state->gmu_registers[3], false);
>>  }
>>
>>  static struct msm_gpu_state_bo *a6xx_snapshot_gmu_bo(
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
>> index dd4c28a8d923..e545106c70be 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h
>> @@ -363,6 +363,9 @@ static const u32 a6xx_gmu_cx_registers[] = {
>>         0x51e0, 0x51e2, 0x51f0, 0x51f0, 0x5200, 0x5201,
>>         /* GMU AO */
>>         0x9300, 0x9316, 0x9400, 0x9400,
>> +};
>> +
>> +static const u32 a6xx_gmu_gpucc_registers[] = {
>>         /* GPU CC */
>>         0x9800, 0x9812, 0x9840, 0x9852, 0x9c00, 0x9c04, 0x9c07, 0x9c0b,
>>         0x9c15, 0x9c1c, 0x9c1e, 0x9c2d, 0x9c3c, 0x9c3d, 0x9c3f, 0x9c40,
>> @@ -373,6 +376,17 @@ static const u32 a6xx_gmu_cx_registers[] = {
>>         0xbc00, 0xbc16, 0xbc20, 0xbc27,
>>  };
>>
>> +static const u32 a621_gmu_gpucc_registers[] = {
>> +       /* GPU CC */
>> +       0x9800, 0x980e, 0x9c00, 0x9c0e, 0xb000, 0xb004, 0xb400, 0xb404,
>> +       0xb800, 0xb804, 0xbc00, 0xbc05, 0xbc14, 0xbc1d, 0xbc2a, 0xbc30,
>> +       0xbc32, 0xbc32, 0xbc41, 0xbc55, 0xbc66, 0xbc68, 0xbc78, 0xbc7a,
>> +       0xbc89, 0xbc8a, 0xbc9c, 0xbc9e, 0xbca0, 0xbca3, 0xbcb3, 0xbcb5,
>> +       0xbcc5, 0xbcc7, 0xbcd6, 0xbcd8, 0xbce8, 0xbce9, 0xbcf9, 0xbcfc,
>> +       0xbd0b, 0xbd0c, 0xbd1c, 0xbd1e, 0xbd40, 0xbd70, 0xbe00, 0xbe16,
>> +       0xbe20, 0xbe2d,
>> +};
>> +
>>  static const u32 a6xx_gmu_cx_rscc_registers[] = {
>>         /* GPU RSCC */
>>         0x008c, 0x008c, 0x0101, 0x0102, 0x0340, 0x0342, 0x0344, 0x0347,
>> @@ -386,6 +400,9 @@ static const struct a6xx_registers a6xx_gmu_reglist[] = {
>>         REGS(a6xx_gmu_gx_registers, 0, 0),
>>  };
>>
>> +static const struct a6xx_registers a6xx_gpucc_reg = REGS(a6xx_gmu_gpucc_registers, 0, 0);
>> +static const struct a6xx_registers a621_gpucc_reg = REGS(a621_gmu_gpucc_registers, 0, 0);
>> +
>>  static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu);
>>  static u32 a7xx_get_cp_roq_size(struct msm_gpu *gpu);
>>
>>
>> --
>> 2.45.2
>>