[PATCH v5 0/2] drm/msm/dsi/phy: Improvements around concurrent PHY_CMN_CLK_CFG[01]

[Dmitry Baryshkov]

On Wed, 19 Feb 2025 17:23:31 +0100, Krzysztof Kozlowski wrote:
> Changes in v5:
> - Drop applied patches 1-3
> - Split part touching pll_7nm_register() from last (#4) patch to new patch
>    - Thus: new patch #1 in new numbering.
> - Link to v4: https://lore.kernel.org/r/20250217-drm-msm-phy-pll-cfg-reg-v4-0-106b0d1df51e@linaro.org
> 
> Changes in v4:
> - Add tags
> - Patch #4: Add mising bitfield.h include
> - One more FIELD_GET and DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL (Dmitry)
> - Link to v3: https://lore.kernel.org/r/20250214-drm-msm-phy-pll-cfg-reg-v3-0-0943b850722c@linaro.org
> 
> [...]

Applied, thanks!

[1/2] drm/msm/dsi/phy: Use dsi_pll_cmn_clk_cfg1_update() when registering PLL
      https://gitlab.freedesktop.org/lumag/msm/-/commit/de36ea80b303
[2/2] drm/msm/dsi/phy: Define PHY_CMN_CLK_CFG[01] bitfields and simplify saving
      https://gitlab.freedesktop.org/lumag/msm/-/commit/0699018b41d7

Best regards,
-- 
Dmitry Baryshkov <dmitry.baryshkov at linaro.org>