[PATCH v2 03/10] dt-bindings: display: msm: document DSI controller and phy on SA8775P

[Dmitry Baryshkov]

On Tue, Mar 11, 2025 at 05:54:38PM +0530, Ayushi Makhija wrote:
> Document DSI controller and phy on SA8775P platform.
> 
> Signed-off-by: Ayushi Makhija <quic_amakhija at quicinc.com>
> ---
>  .../display/msm/qcom,sa8775p-mdss.yaml        | 188 ++++++++++++++++++
>  1 file changed, 188 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> index a90a8b3f1a9e..628ca68871f4 100644
> --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml
> @@ -52,6 +52,26 @@ patternProperties:
>          items:
>            - const: qcom,sa8775p-dp
>  
> +  "^dsi@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +
> +    properties:
> +      compatible:
> +        items:
> +          - const: qcom,sa8775p-dsi-ctrl
> +          - const: qcom,mdss-dsi-ctrl
> +
> +  "^phy@[0-9a-f]+$":
> +    type: object
> +    additionalProperties: true
> +
> +    properties:
> +      compatible:
> +        enum:
> +          - qcom,sa8775p-dsi-phy-5nm
> +          - qcom,sa8775p-edp-phy

This does more than is written in the commit message: it also adds eDP
PHY as a possible child. Please expand the commit message to account for
that.

> +
>  required:
>    - compatible
>  
> @@ -131,6 +151,20 @@ examples:
>                          remote-endpoint = <&mdss0_dp0_in>;
>                      };
>                  };
> +
> +                port at 1 {
> +                    reg = <1>;
> +                    dpu_intf1_out: endpoint {
> +                        remote-endpoint = <&mdss0_dsi0_in>;
> +                    };
> +                };
> +
> +                port at 2 {
> +                    reg = <2>;
> +                    dpu_intf2_out: endpoint {
> +                        remote-endpoint = <&mdss0_dsi1_in>;
> +                    };
> +                };
>              };
>  
>              mdss0_mdp_opp_table: opp-table {
> @@ -158,6 +192,160 @@ examples:
>              };
>          };
>  
> +        dsi at ae94000 {
> +            compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> +            reg = <0x0ae94000 0x400>;
> +            reg-names = "dsi_ctrl";
> +
> +            interrupt-parent = <&mdss>;
> +            interrupts = <4>;
> +
> +            clocks = <&dispc_byte_clk>,
> +                     <&dispcc_intf_clk>,
> +                     <&dispcc_pclk>,
> +                     <&dispcc_esc_clk>,
> +                     <&dispcc_ahb_clk>,
> +                     <&gcc_bus_clk>;
> +            clock-names = "byte",
> +                          "byte_intf",
> +                          "pixel",
> +                          "core",
> +                          "iface",
> +                          "bus";
> +            assigned-clocks = <&dispcc_byte_clk>,
> +                              <&dispcc_pclk>;
> +            assigned-clock-parents = <&mdss0_dsi0_phy 0>, <&mdss0_dsi0_phy 1>;
> +            phys = <&mdss0_dsi0_phy>;
> +
> +            operating-points-v2 = <&dsi0_opp_table>;
> +            power-domains = <&rpmhpd SA8775P_MMCX>;
> +
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                port at 0 {
> +                    reg = <0>;
> +                    mdss0_dsi0_in: endpoint {
> +                        remote-endpoint = <&dpu_intf1_out>;
> +                    };
> +                };
> +
> +                port at 1 {
> +                    reg = <1>;
> +                    mdss0_dsi0_out: endpoint { };
> +                };
> +            };
> +
> +            dsi0_opp_table: opp-table {
> +                compatible = "operating-points-v2";
> +
> +                opp-358000000 {
> +                    opp-hz = /bits/ 64 <358000000>;
> +                    required-opps = <&rpmhpd_opp_svs_l1>;
> +                };
> +            };
> +        };
> +
> +        mdss0_dsi0_phy: phy at ae94400 {
> +            compatible = "qcom,sa8775p-dsi-phy-5nm";
> +            reg = <0x0ae94400 0x200>,
> +                  <0x0ae94600 0x280>,
> +                  <0x0ae94900 0x27c>;
> +            reg-names = "dsi_phy",
> +                        "dsi_phy_lane",
> +                        "dsi_pll";
> +
> +            #clock-cells = <1>;
> +            #phy-cells = <0>;
> +
> +            clocks = <&dispcc_iface_clk>,
> +                     <&rpmhcc_ref_clk>;
> +            clock-names = "iface", "ref";
> +
> +            vdds-supply = <&vreg_dsi_supply>;
> +        };
> +
> +        dsi at ae96000 {
> +            compatible = "qcom,sa8775p-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> +            reg = <0x0ae96000 0x400>;
> +            reg-names = "dsi_ctrl";
> +
> +            interrupt-parent = <&mdss>;
> +            interrupts = <4>;
> +
> +            clocks = <&dispc_byte_clk>,
> +                     <&dispcc_intf_clk>,
> +                     <&dispcc_pclk>,
> +                     <&dispcc_esc_clk>,
> +                     <&dispcc_ahb_clk>,
> +                     <&gcc_bus_clk>;
> +            clock-names = "byte",
> +                          "byte_intf",
> +                          "pixel",
> +                          "core",
> +                          "iface",
> +                          "bus";
> +            assigned-clocks = <&dispcc_byte_clk>,
> +                              <&dispcc_pclk>;
> +            assigned-clock-parents = <&mdss0_dsi1_phy 0>, <&mdss0_dsi1_phy 1>;
> +            phys = <&mdss0_dsi1_phy>;
> +
> +            operating-points-v2 = <&dsi1_opp_table>;
> +            power-domains = <&rpmhpd SA8775P_MMCX>;
> +
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            ports {
> +                #address-cells = <1>;
> +                #size-cells = <0>;
> +
> +                port at 0 {
> +                    reg = <0>;
> +                    mdss0_dsi1_in: endpoint {
> +                        remote-endpoint = <&dpu_intf2_out>;
> +                    };
> +                };
> +
> +                port at 1 {
> +                    reg = <1>;
> +                    mdss0_dsi1_out: endpoint { };
> +                };
> +            };
> +
> +            dsi1_opp_table: opp-table {
> +                compatible = "operating-points-v2";
> +
> +                opp-358000000 {
> +                    opp-hz = /bits/ 64 <358000000>;
> +                    required-opps = <&rpmhpd_opp_svs_l1>;
> +                };
> +            };
> +        };
> +
> +        mdss0_dsi1_phy: phy at ae96400 {
> +            compatible = "qcom,sa8775p-dsi-phy-5nm";
> +            reg = <0x0ae96400 0x200>,
> +                  <0x0ae96600 0x280>,
> +                  <0x0ae96900 0x27c>;
> +            reg-names = "dsi_phy",
> +                        "dsi_phy_lane",
> +                        "dsi_pll";
> +
> +            #clock-cells = <1>;
> +            #phy-cells = <0>;
> +
> +            clocks = <&dispcc_iface_clk>,
> +                     <&rpmhcc_ref_clk>;
> +            clock-names = "iface", "ref";
> +
> +            vdds-supply = <&vreg_dsi_supply>;
> +        };
> +
>          displayport-controller at af54000 {
>              compatible = "qcom,sa8775p-dp";
>  
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry