[igt-dev] [PATCH i-g-t 09/20] tests/psr: Check for PSR entry more often and only for a second.

[Dhinakaran Pandiyan]

On Thu, 2018-04-12 at 13:25 +0200, Katarzyna Dec wrote:
> On Tue, Apr 10, 2018 at 07:37:21PM -0700, Dhinakaran Pandiyan wrote:
> > 1 second interval is too long, check every 100ms.
> > 
> > PSR gets enabled when pipes are enabled on BDW+. It shouldn't take
> > 5 seconds even on VLV/CHV, where we delay a bit. Limit the checks to a
> > 1 second total wait, so that we know if the delay is longer.
> > 
> > Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> > ---
> >  tests/kms_psr_sink_crc.c | 6 ++++--
> >  1 file changed, 4 insertions(+), 2 deletions(-)
> > 
> > diff --git a/tests/kms_psr_sink_crc.c b/tests/kms_psr_sink_crc.c
> > index e04e0f6a..d940ec89 100644
> > --- a/tests/kms_psr_sink_crc.c
> > +++ b/tests/kms_psr_sink_crc.c
> > @@ -214,11 +214,13 @@ static bool psr_enabled(data_t *data)
> >  
> >  static bool wait_psr_entry(data_t *data)
> >  {
> > -	int timeout = 5;
> > +	int timeout = 10;
> > +
> >  	while (timeout--) {
> >  		if (psr_enabled(data))
> >  			return true;
> > -		sleep(1);
> > +		usleep(100000);
>  Is this change based on documentation or on some experimental values?

The order of the delay is in 100 micro seconds. As we don't know the
exact value, checking every 100 us made sense. The total delay of 1
second however is probably not enough on VLV/CHV. 

Anyway this optimization isn't necessary now as I am thinking of killing
PSR support of VLV/CHV in the driver. Please ignore this patch.

>                                                                                                                                           
>   Kasia
> > +		igt_debug("Waiting for PSR entry %d ms\n", (10-timeout)*100);
> >  	}
> >  	return false;
> >  }
> > -- 
> > 2.14.1
> > 
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