[igt-dev] [PATCH i-g-t 2/5] lib/gen6_render.h: Use gen6 definitions where it is possible
Lukasz Kalamarz
lukasz.kalamarz at intel.com
Fri Jun 8 11:38:52 UTC 2018
As long as it is applicable, We should use in our libs
definitions from oldest gen if it is possible. This patch
reuse gen6 definitons if registers/fields/shifts that were
reintroduced in other genX_render headers.
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz at intel.com>
Cc: Katarzyna Dec <katarzyna.dec at intel.com>
Cc: Antonio Argenziano <antonio.argenziano at intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
Cc: Ewelina Musial <ewelina.musial at intel.com>
---
lib/rendercopy_gen7.c | 108 +++++++++++++-------------
lib/rendercopy_gen8.c | 4 +-
lib/rendercopy_gen9.c | 4 +-
tools/null_state_gen/intel_renderstate_gen7.c | 108 +++++++++++++-------------
tools/null_state_gen/intel_renderstate_gen8.c | 10 +--
tools/null_state_gen/intel_renderstate_gen9.c | 10 +--
6 files changed, 122 insertions(+), 122 deletions(-)
diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
index 82e33288..bdcf3c7b 100644
--- a/lib/rendercopy_gen7.c
+++ b/lib/rendercopy_gen7.c
@@ -101,35 +101,35 @@ gen7_bind_buf(struct intel_batchbuffer *batch,
static void
gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_VERTEX_ELEMENTS |
+ OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
((2 * (1 + 2)) + 1 - 2));
- OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
- SURFACEFORMAT_R32G32B32A32_FLOAT << GEN7_VE0_FORMAT_SHIFT |
- 0 << GEN7_VE0_OFFSET_SHIFT);
+ OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
+ 0 << VE0_OFFSET_SHIFT);
- OUT_BATCH(GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_0_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_1_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* x,y */
- OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
- SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
- 0 << GEN7_VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
- GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
- GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
+ 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
+ OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* s,t */
- OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
- SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
- 4 << GEN7_VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
- GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
- GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
+ 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
+ OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
}
static uint32_t
@@ -166,11 +166,11 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
int width, int height,
uint32_t offset)
{
- OUT_BATCH(GEN7_3DSTATE_VERTEX_BUFFERS | (5 - 2));
- OUT_BATCH(0 << GEN7_VB0_BUFFER_INDEX_SHIFT |
- GEN7_VB0_VERTEXDATA |
+ OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT |
+ VB0_VERTEXDATA |
GEN7_VB0_ADDRESS_MODIFY_ENABLE |
- 4 * 2 << GEN7_VB0_BUFFER_PITCH_SHIFT);
+ 4 * 2 << VB0_BUFFER_PITCH_SHIFT);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
OUT_BATCH(~0);
@@ -207,7 +207,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch,
static void
gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
{
- OUT_BATCH(GEN7_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0);
OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
OUT_BATCH(0);
@@ -216,13 +216,13 @@ gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst
static uint32_t
gen7_create_blend_state(struct intel_batchbuffer *batch)
{
- struct gen7_blend_state *blend;
+ struct gen6_blend_state *blend;
blend = intel_batchbuffer_subdata_alloc(batch, sizeof(*blend), 64);
- blend->blend0.dest_blend_factor = GEN7_BLENDFACTOR_ZERO;
- blend->blend0.source_blend_factor = GEN7_BLENDFACTOR_ONE;
- blend->blend0.blend_func = GEN7_BLENDFUNCTION_ADD;
+ blend->blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
+ blend->blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
+ blend->blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
blend->blend1.post_blend_clamp_enable = 1;
blend->blend1.pre_blend_clamp_enable = 1;
@@ -232,7 +232,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch)
static void
gen7_emit_state_base_address(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
OUT_BATCH(0);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
@@ -248,7 +248,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch)
static uint32_t
gen7_create_cc_viewport(struct intel_batchbuffer *batch)
{
- struct gen7_cc_viewport *vp;
+ struct gen6_cc_viewport *vp;
vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32);
vp->min_depth = -1.e35;
@@ -275,12 +275,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch)
ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 32);
- ss->ss0.min_filter = GEN7_MAPFILTER_NEAREST;
- ss->ss0.mag_filter = GEN7_MAPFILTER_NEAREST;
+ ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
+ ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss3.r_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
- ss->ss3.s_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
- ss->ss3.t_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
+ ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
ss->ss3.non_normalized_coord = 1;
@@ -297,13 +297,13 @@ gen7_emit_sampler(struct intel_batchbuffer *batch, uint32_t sampler_off)
static void
gen7_emit_multisample(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE | (4 - 2));
- OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
- GEN7_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
+ GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN7_3DSTATE_SAMPLE_MASK | (2 - 2));
+ OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
OUT_BATCH(1);
}
@@ -335,7 +335,7 @@ gen7_emit_urb(struct intel_batchbuffer *batch)
static void
gen7_emit_vs(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_VS | (6 - 2));
+ OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
OUT_BATCH(0); /* no VS kernel */
OUT_BATCH(0);
OUT_BATCH(0);
@@ -378,7 +378,7 @@ gen7_emit_ds(struct intel_batchbuffer *batch)
static void
gen7_emit_gs(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_GS | (7 - 2));
+ OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
OUT_BATCH(0); /* no GS kernel */
OUT_BATCH(0);
OUT_BATCH(0);
@@ -398,10 +398,10 @@ gen7_emit_streamout(struct intel_batchbuffer *batch)
static void
gen7_emit_sf(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_SF | (7 - 2));
+ OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
OUT_BATCH(0);
- OUT_BATCH(GEN7_3DSTATE_SF_CULL_NONE);
- OUT_BATCH(2 << GEN7_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
+ OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
+ OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -454,7 +454,7 @@ gen7_emit_ps(struct intel_batchbuffer *batch, uint32_t kernel_off)
static void
gen7_emit_clip(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_CLIP | (4 - 2));
+ OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0); /* pass-through */
OUT_BATCH(0);
@@ -466,7 +466,7 @@ gen7_emit_clip(struct intel_batchbuffer *batch)
static void
gen7_emit_wm(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_WM | (3 - 2));
+ OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
OUT_BATCH(0);
@@ -476,8 +476,8 @@ static void
gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
{
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
- OUT_BATCH(SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
- GEN7_DEPTHFORMAT_D32_FLOAT << GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
+ OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
+ GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
OUT_BATCH(0); /* disable depth, stencil and hiz */
OUT_BATCH(0);
OUT_BATCH(0);
@@ -520,7 +520,7 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch,
igt_assert(batch->ptr < &batch->buffer[4095]);
batch->ptr = batch->buffer;
- OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
gen7_emit_state_base_address(batch);
gen7_emit_multisample(batch);
@@ -546,8 +546,8 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch,
gen7_emit_binding_table(batch, src, dst, ps_binding_table);
gen7_emit_drawing_rectangle(batch, dst);
- OUT_BATCH(GEN7_3DPRIMITIVE | (7 - 2));
- OUT_BATCH(GEN7_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
+ OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2));
+ OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
OUT_BATCH(3);
OUT_BATCH(0);
OUT_BATCH(1); /* single instance */
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index b60d18a7..a328e2bd 100644
--- a/lib/rendercopy_gen8.c
+++ b/lib/rendercopy_gen8.c
@@ -622,7 +622,7 @@ gen8_emit_hs(struct intel_batchbuffer *batch) {
static void
gen8_emit_gs(struct intel_batchbuffer *batch) {
- OUT_BATCH(GEN7_3DSTATE_CONSTANT_GS | (11 - 2));
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (11 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -634,7 +634,7 @@ gen8_emit_gs(struct intel_batchbuffer *batch) {
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN7_3DSTATE_GS | (10-2));
+ OUT_BATCH(GEN6_3DSTATE_GS | (10-2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index ea69b95f..d1d72594 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -619,7 +619,7 @@ gen8_emit_hs(struct intel_batchbuffer *batch) {
static void
gen8_emit_gs(struct intel_batchbuffer *batch) {
- OUT_BATCH(GEN7_3DSTATE_CONSTANT_GS | (11-2));
+ OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (11-2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -631,7 +631,7 @@ gen8_emit_gs(struct intel_batchbuffer *batch) {
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN7_3DSTATE_GS | (10-2));
+ OUT_BATCH(GEN6_3DSTATE_GS | (10-2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
diff --git a/tools/null_state_gen/intel_renderstate_gen7.c b/tools/null_state_gen/intel_renderstate_gen7.c
index ea5cfc29..75ee9d6d 100644
--- a/tools/null_state_gen/intel_renderstate_gen7.c
+++ b/tools/null_state_gen/intel_renderstate_gen7.c
@@ -49,36 +49,36 @@ gen7_bind_buf_null(struct intel_batchbuffer *batch)
static void
gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_VERTEX_ELEMENTS |
+ OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
((2 * (1 + 2)) + 1 - 2));
- OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
+ OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
SURFACEFORMAT_R32G32B32A32_FLOAT <<
- GEN7_VE0_FORMAT_SHIFT |
- 0 << GEN7_VE0_OFFSET_SHIFT);
+ VE0_FORMAT_SHIFT |
+ 0 << VE0_OFFSET_SHIFT);
- OUT_BATCH(GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_0_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_1_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* x,y */
- OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
- SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
- 0 << GEN7_VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
- GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
- GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
+ 0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
+ OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* s,t */
- OUT_BATCH(0 << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID |
- SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT |
- 4 << GEN7_VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT |
- GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT |
- GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT |
- GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
+ 4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
+ OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
}
static uint32_t
@@ -95,12 +95,12 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch)
offset = gen7_create_vertex_buffer(batch);
- OUT_BATCH(GEN7_3DSTATE_VERTEX_BUFFERS | (5 - 2));
- OUT_BATCH(0 << GEN7_VB0_BUFFER_INDEX_SHIFT |
- GEN7_VB0_VERTEXDATA |
+ OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT |
+ VB0_VERTEXDATA |
GEN7_VB0_ADDRESS_MODIFY_ENABLE |
- GEN7_VB0_NULL_VERTEX_BUFFER |
- 4*2 << GEN7_VB0_BUFFER_PITCH_SHIFT);
+ VB0_NULL_VERTEX_BUFFER |
+ 4*2 << VB0_BUFFER_PITCH_SHIFT);
OUT_RELOC_STATE(batch, I915_GEM_DOMAIN_VERTEX, 0, offset);
OUT_BATCH(~0);
@@ -130,7 +130,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch)
static void
gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
/* Purposedly set min > max for null rectangle */
OUT_BATCH(0xffffffff);
OUT_BATCH(0 | 0);
@@ -140,12 +140,12 @@ gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch)
static uint32_t
gen7_create_blend_state(struct intel_batchbuffer *batch)
{
- struct gen7_blend_state blend;
+ struct gen6_blend_state blend;
memset(&blend, 0, sizeof(blend));
- blend.blend0.dest_blend_factor = GEN7_BLENDFACTOR_ZERO;
- blend.blend0.source_blend_factor = GEN7_BLENDFACTOR_ONE;
- blend.blend0.blend_func = GEN7_BLENDFUNCTION_ADD;
+ blend.blend0.dest_blend_factor = GEN6_BLENDFACTOR_ZERO;
+ blend.blend0.source_blend_factor = GEN6_BLENDFACTOR_ONE;
+ blend.blend0.blend_func = GEN6_BLENDFUNCTION_ADD;
blend.blend1.post_blend_clamp_enable = 1;
blend.blend1.pre_blend_clamp_enable = 1;
@@ -155,7 +155,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch)
static void
gen7_emit_state_base_address(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
OUT_BATCH(0);
OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
@@ -171,7 +171,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch)
static uint32_t
gen7_create_cc_viewport(struct intel_batchbuffer *batch)
{
- struct gen7_cc_viewport vp;
+ struct gen6_cc_viewport vp;
memset(&vp, 0, sizeof(vp));
vp.min_depth = -1.e35;
@@ -196,12 +196,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch)
struct gen7_sampler_state ss;
memset(&ss, 0, sizeof(ss));
- ss.ss0.min_filter = GEN7_MAPFILTER_NEAREST;
- ss.ss0.mag_filter = GEN7_MAPFILTER_NEAREST;
+ ss.ss0.min_filter = GEN6_MAPFILTER_NEAREST;
+ ss.ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
- ss.ss3.r_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
- ss.ss3.s_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
- ss.ss3.t_wrap_mode = GEN7_TEXCOORDMODE_CLAMP;
+ ss.ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss.ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss.ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
ss.ss3.non_normalized_coord = 1;
@@ -218,13 +218,13 @@ gen7_emit_sampler(struct intel_batchbuffer *batch)
static void
gen7_emit_multisample(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE | (4 - 2));
- OUT_BATCH(GEN7_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
- GEN7_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (4 - 2));
+ OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
+ GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_1); /* 1 sample/pixel */
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN7_3DSTATE_SAMPLE_MASK | (2 - 2));
+ OUT_BATCH(GEN6_3DSTATE_SAMPLE_MASK | (2 - 2));
OUT_BATCH(1);
}
@@ -256,7 +256,7 @@ gen7_emit_urb(struct intel_batchbuffer *batch)
static void
gen7_emit_vs(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_VS | (6 - 2));
+ OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
OUT_BATCH(0); /* no VS kernel */
OUT_BATCH(0);
OUT_BATCH(0);
@@ -299,7 +299,7 @@ gen7_emit_ds(struct intel_batchbuffer *batch)
static void
gen7_emit_gs(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_GS | (7 - 2));
+ OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
OUT_BATCH(0); /* no GS kernel */
OUT_BATCH(0);
OUT_BATCH(0);
@@ -319,10 +319,10 @@ gen7_emit_streamout(struct intel_batchbuffer *batch)
static void
gen7_emit_sf(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_SF | (7 - 2));
+ OUT_BATCH(GEN6_3DSTATE_SF | (7 - 2));
OUT_BATCH(0);
- OUT_BATCH(GEN7_3DSTATE_SF_CULL_NONE);
- OUT_BATCH(2 << GEN7_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
+ OUT_BATCH(GEN6_3DSTATE_SF_CULL_NONE);
+ OUT_BATCH(2 << GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
@@ -379,7 +379,7 @@ gen7_emit_ps(struct intel_batchbuffer *batch)
static void
gen7_emit_clip(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_CLIP | (4 - 2));
+ OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
OUT_BATCH(0);
OUT_BATCH(0); /* pass-through */
OUT_BATCH(0);
@@ -391,7 +391,7 @@ gen7_emit_clip(struct intel_batchbuffer *batch)
static void
gen7_emit_wm(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_3DSTATE_WM | (3 - 2));
+ OUT_BATCH(GEN6_3DSTATE_WM | (3 - 2));
OUT_BATCH(GEN7_WM_DISPATCH_ENABLE |
GEN7_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
OUT_BATCH(0);
@@ -402,7 +402,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
{
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
OUT_BATCH(SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
- GEN7_DEPTHFORMAT_D32_FLOAT <<
+ GEN6_DEPTHFORMAT_D32_FLOAT <<
GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
OUT_BATCH(0); /* disable depth, stencil and hiz */
OUT_BATCH(0);
@@ -417,7 +417,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
void gen7_setup_null_render_state(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN7_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
gen7_emit_state_base_address(batch);
gen7_emit_multisample(batch);
@@ -442,8 +442,8 @@ void gen7_setup_null_render_state(struct intel_batchbuffer *batch)
gen7_emit_binding_table(batch);
gen7_emit_drawing_rectangle(batch);
- OUT_BATCH(GEN7_3DPRIMITIVE | (7 - 2));
- OUT_BATCH(GEN7_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
+ OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2));
+ OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
OUT_BATCH(3);
OUT_BATCH(0);
OUT_BATCH(1); /* single instance */
diff --git a/tools/null_state_gen/intel_renderstate_gen8.c b/tools/null_state_gen/intel_renderstate_gen8.c
index 6a309d43..08def120 100644
--- a/tools/null_state_gen/intel_renderstate_gen8.c
+++ b/tools/null_state_gen/intel_renderstate_gen8.c
@@ -346,7 +346,7 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
gen8_emit_vs(batch);
gen8_emit_hs(batch);
- OUT_CMD(GEN7_3DSTATE_GS, 10);
+ OUT_CMD(GEN6_3DSTATE_GS, 10);
OUT_CMD(GEN7_3DSTATE_STREAMOUT, 5);
OUT_CMD(GEN7_3DSTATE_DS, 9);
OUT_CMD(GEN6_3DSTATE_CLIP, 4);
@@ -368,8 +368,8 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
OUT_CMD(GEN6_3DSTATE_CONSTANT_VS, 11);
OUT_CMD(GEN7_3DSTATE_CONSTANT_HS, 11);
OUT_CMD(GEN7_3DSTATE_CONSTANT_DS, 11);
- OUT_CMD(GEN7_3DSTATE_CONSTANT_GS, 11);
- OUT_CMD(GEN7_3DSTATE_CONSTANT_PS, 11);
+ OUT_CMD(GEN6_3DSTATE_CONSTANT_GS, 11);
+ OUT_CMD(GEN6_3DSTATE_CONSTANT_PS, 11);
OUT_CMD(GEN8_3DSTATE_VF_INSTANCING, 3);
OUT_CMD(GEN8_3DSTATE_VF_SGVS, 2);
@@ -399,8 +399,8 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
OUT_CMD(GEN7_3DSTATE_CLEAR_PARAMS, 3);
OUT_CMD(GEN6_3DSTATE_MONOFILTER_SIZE, 2);
OUT_CMD(GEN8_3DSTATE_MULTISAMPLE, 2);
- OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_OFFSET, 2);
- OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_PATTERN, 33);
+ OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_OFFSET, 2);
+ OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_PATTERN, 33);
OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0, 16 + 1);
OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1, 16 + 1);
OUT_CMD(GEN6_3DSTATE_INDEX_BUFFER, 5);
diff --git a/tools/null_state_gen/intel_renderstate_gen9.c b/tools/null_state_gen/intel_renderstate_gen9.c
index a0b7d8ad..1b77e552 100644
--- a/tools/null_state_gen/intel_renderstate_gen9.c
+++ b/tools/null_state_gen/intel_renderstate_gen9.c
@@ -369,7 +369,7 @@ void gen9_setup_null_render_state(struct intel_batchbuffer *batch)
gen8_emit_vs(batch);
gen8_emit_hs(batch);
- OUT_CMD(GEN7_3DSTATE_GS, 10);
+ OUT_CMD(GEN6_3DSTATE_GS, 10);
OUT_CMD(GEN7_3DSTATE_STREAMOUT, 5);
OUT_CMD(GEN7_3DSTATE_DS, 11); /* Check w/ Gen8 code */
OUT_CMD(GEN6_3DSTATE_CLIP, 4);
@@ -396,8 +396,8 @@ void gen9_setup_null_render_state(struct intel_batchbuffer *batch)
OUT_CMD(GEN6_3DSTATE_CONSTANT_VS, 11);
OUT_CMD(GEN7_3DSTATE_CONSTANT_HS, 11);
OUT_CMD(GEN7_3DSTATE_CONSTANT_DS, 11);
- OUT_CMD(GEN7_3DSTATE_CONSTANT_GS, 11);
- OUT_CMD(GEN7_3DSTATE_CONSTANT_PS, 11);
+ OUT_CMD(GEN6_3DSTATE_CONSTANT_GS, 11);
+ OUT_CMD(GEN6_3DSTATE_CONSTANT_PS, 11);
OUT_CMD(GEN8_3DSTATE_VF_INSTANCING, 3);
OUT_CMD(GEN8_3DSTATE_VF_SGVS, 2);
@@ -430,8 +430,8 @@ void gen9_setup_null_render_state(struct intel_batchbuffer *batch)
OUT_CMD(GEN7_3DSTATE_CLEAR_PARAMS, 3);
OUT_CMD(GEN6_3DSTATE_MONOFILTER_SIZE, 2);
OUT_CMD(GEN8_3DSTATE_MULTISAMPLE, 2);
- OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_OFFSET, 2);
- OUT_CMD(GEN8_3DSTATE_POLY_STIPPLE_PATTERN, 1 + 32);
+ OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_OFFSET, 2);
+ OUT_CMD(GEN6_3DSTATE_POLY_STIPPLE_PATTERN, 1 + 32);
OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0, 1 + 16);
OUT_CMD(GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1, 1 + 16);
OUT_CMD(GEN6_3DSTATE_INDEX_BUFFER, 5);
--
2.14.3
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