[igt-dev] [PATCH i-g-t v1] Data Port Cache Coherency tests.

[Joonas Lahtinen]

Quoting Tomasz Lis (2018-06-20 18:14:38)
> This adds a new test binary, containing tests for the Data Port Coherency
> option. The tests check whether the option value is stored properly on the
> kernel side, but also whether is is correctly set to proper GPU register.

I'm fairly sure there already was review feedback that simply checking
the register state is not a good IGT test.

IGT tests make sure that whatever uAPI the kernel has, the promised effects
of that uAPI do not get broken. And the promise for cache coherency uAPI
for surely isn't that some register value gets written, it's that the
cache coherency is traded with some performance. The chicken bits or the
whole implementation of the feature might be turned upside down, but as
long as the userspace is still working, userspace should not care.

So the chicken bit setting should be scrapped, and actual cache
coherency observed. It might be a worthy kernel selftest that register
writes stick and remain over sleep states as a generic thing, but not
here.

If you don't address the feedback given, but hammer the mailing list
without addressing it, don't expect further feedback.

Regards, Joonas