[igt-dev] [PATCH i-g-t v6 2/2] tests: add slice power programming test
Lionel Landwerlin
lionel.g.landwerlin at intel.com
Fri May 25 15:57:04 UTC 2018
Thanks, all applied.
On 25/05/18 16:41, Chris Wilson wrote:
> Quoting Lionel Landwerlin (2018-05-25 16:26:40)
>> Verifies that the kernel programs slices correctly based by reading
>> the value of PWR_CLK_STATE register or MI_SET_PREDICATE on platforms
>> before Cannonlake.
>>
>> v2: Add subslice tests (Lionel)
>> Use MI_SET_PREDICATE for further verification when available (Lionel)
>>
>> v3: Rename to gem_ctx_rpcs (Lionel)
>>
>> v4: Update kernel API (Lionel)
>> Add 0 value test (Lionel)
>> Exercise invalid values (Lionel)
>>
>> v5: Add perf tests (Lionel)
>>
>> v6: Add new sysfs entry tests (Lionel)
>>
>> v7: Test rsvd fields
>> Update for kernel series changes
>>
>> v8: Drop test_no_sseu_support() test (Kelvin)
>> Drop drm_intel_*() apis (Chris)
>>
>> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
>> ---
>> tests/Makefile.sources | 1 +
>> tests/gem_ctx_param.c | 4 +-
>> tests/gem_ctx_sseu.c | 881 +++++++++++++++++++++++++++++++++++++++++
>> tests/meson.build | 1 +
>> 4 files changed, 886 insertions(+), 1 deletion(-)
>> create mode 100644 tests/gem_ctx_sseu.c
>>
>> diff --git a/tests/Makefile.sources b/tests/Makefile.sources
>> index ad62611f..fd44b720 100644
>> --- a/tests/Makefile.sources
>> +++ b/tests/Makefile.sources
>> @@ -60,6 +60,7 @@ TESTS_progs = \
>> gem_ctx_exec \
>> gem_ctx_isolation \
>> gem_ctx_param \
>> + gem_ctx_sseu \
>> gem_ctx_switch \
>> gem_ctx_thrash \
>> gem_double_irq_loop \
>> diff --git a/tests/gem_ctx_param.c b/tests/gem_ctx_param.c
>> index c46fd709..af1afeaa 100644
>> --- a/tests/gem_ctx_param.c
>> +++ b/tests/gem_ctx_param.c
>> @@ -294,11 +294,13 @@ igt_main
>> set_priority(fd);
>> }
>>
>> + /* I915_CONTEXT_PARAM_SSEU tests are located in gem_ctx_sseu.c */
>> +
>> /* NOTE: This testcase intentionally tests for the next free parameter
>> * to catch ABI extensions. Don't "fix" this testcase without adding all
>> * the tests for the new param first.
>> */
>> - arg.param = I915_CONTEXT_PARAM_PRIORITY + 1;
>> + arg.param = I915_CONTEXT_PARAM_SSEU + 1;
>>
>> igt_subtest("invalid-param-get") {
>> arg.ctx_id = ctx;
>> diff --git a/tests/gem_ctx_sseu.c b/tests/gem_ctx_sseu.c
>> new file mode 100644
>> index 00000000..75095a6b
>> --- /dev/null
>> +++ b/tests/gem_ctx_sseu.c
>> @@ -0,0 +1,881 @@
>> +/*
>> + * Copyright © 2017 Intel Corporation
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice (including the next
>> + * paragraph) shall be included in all copies or substantial portions of the
>> + * Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
>> + * IN THE SOFTWARE.
>> + *
>> + * Authors:
>> + * Lionel Landwerlin <lionel.g.landwerlin at intel.com>
>> + *
>> + */
>> +
>> +#include "igt.h"
>> +#include <stdio.h>
>> +#include <stdlib.h>
>> +#include <string.h>
>> +#include <unistd.h>
>> +#include <fcntl.h>
>> +#include <signal.h>
>> +#include <errno.h>
>> +#include <time.h>
>> +#include <sys/wait.h>
>> +
>> +#include "igt_sysfs.h"
>> +#include "ioctl_wrappers.h"
>> +
>> +IGT_TEST_DESCRIPTION("Test context render powergating programming.");
>> +
>> +#define MI_STORE_REGISTER_MEM (0x24 << 23)
>> +
>> +#define MI_SET_PREDICATE (0x1 << 23)
>> +#define MI_SET_PREDICATE_NOOP_NEVER (0)
>> +#define MI_SET_PREDICATE_1_SLICES (5)
>> +#define MI_SET_PREDICATE_2_SLICES (6)
>> +#define MI_SET_PREDICATE_3_SLICES (7)
>> +
>> +#define GEN8_R_PWR_CLK_STATE 0x20C8
>> +#define GEN8_RPCS_ENABLE (1 << 31)
>> +#define GEN8_RPCS_S_CNT_ENABLE (1 << 18)
>> +#define GEN8_RPCS_S_CNT_SHIFT 15
>> +#define GEN8_RPCS_S_CNT_MASK (0x7 << GEN8_RPCS_S_CNT_SHIFT)
>> +#define GEN8_RPCS_SS_CNT_ENABLE (1 << 11)
>> +#define GEN8_RPCS_SS_CNT_SHIFT 8
>> +#define GEN8_RPCS_SS_CNT_MASK (0x7 << GEN8_RPCS_SS_CNT_SHIFT)
>> +#define GEN8_RPCS_EU_MAX_SHIFT 4
>> +#define GEN8_RPCS_EU_MAX_MASK (0xf << GEN8_RPCS_EU_MAX_SHIFT)
>> +#define GEN8_RPCS_EU_MIN_SHIFT 0
>> +#define GEN8_RPCS_EU_MIN_MASK (0xf << GEN8_RPCS_EU_MIN_SHIFT)
>> +
>> +#define RCS_TIMESTAMP (0x2000 + 0x358)
>> +
>> +static int drm_fd;
>> +static int devid;
>> +static uint64_t device_slice_mask = 0;
>> +static uint64_t device_subslice_mask = 0;
>> +static uint32_t device_slice_count = 0;
>> +static uint32_t device_subslice_count = 0;
>> +
>> +static uint64_t mask_minus_one(uint64_t mask)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
>> + if ((1UL << i) & mask) {
>> + return mask & ~(1UL << i);
>> + }
>> + }
>> +
>> + igt_assert(!"reached");
>> + return 0;
>> +}
>> +
>> +static uint64_t mask_plus_one(uint64_t mask)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < (sizeof(mask) * 8 - 1); i++) {
>> + if (((1UL << i) & mask) == 0) {
>> + return mask | (1UL << i);
>> + }
>> + }
>> +
>> + igt_assert(!"reached");
>> + return 0;
>> +}
>> +
>> +static uint64_t mask_minus(uint64_t mask, int n)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n; i++)
>> + mask = mask_minus_one(mask);
>> +
>> + return mask;
>> +}
>> +
>> +static uint64_t mask_plus(uint64_t mask, int n)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < n; i++)
>> + mask = mask_plus_one(mask);
>> +
>> + return mask;
>> +}
>> +
>> +static uint32_t *
>> +fill_relocation(uint32_t *batch,
>> + struct drm_i915_gem_relocation_entry *reloc,
>> + uint32_t gem_handle, uint32_t delta, /* in bytes */
>> + uint32_t offset, /* in dwords */
>> + uint32_t read_domains, uint32_t write_domains)
>> +{
>> + reloc->target_handle = gem_handle;
>> + reloc->delta = delta;
>> + reloc->offset = offset * sizeof(uint32_t);
>> + reloc->presumed_offset = 0;
>> + reloc->read_domains = read_domains;
>> + reloc->write_domain = write_domains;
>> +
>> + *batch++ = delta;
>> + *batch++ = 0;
>> +
>> + return batch;
>> +}
>> +
>> +
>> +static uint32_t
>> +read_rpcs_reg(uint32_t context,
>> + uint32_t expected_slices)
>> +{
>> + struct drm_i915_gem_execbuffer2 execbuf;
>> + struct drm_i915_gem_exec_object2 obj[2];
>> + struct drm_i915_gem_relocation_entry relocs[2];
>> + uint32_t *batch, *b, *data;
>> + uint32_t rpcs;
>> + int n_relocs = 0;
>> +
>> + memset(obj, 0, sizeof(obj));
>> + obj[0].handle = gem_create(drm_fd, 4096);
>> + obj[1].handle = gem_create(drm_fd, 4096);
>> +
>> + batch = b = gem_mmap__cpu(drm_fd, obj[1].handle, 0, 4096,
>> + PROT_READ | PROT_WRITE);
>> +
>> + if (expected_slices != 0 && intel_gen(devid) < 10) {
>> + *b++ = MI_SET_PREDICATE | (1 - 1) |
>> + (MI_SET_PREDICATE_1_SLICES + expected_slices - 1);
>> + }
>> +
>> + *b++ = MI_STORE_REGISTER_MEM | (4 - 2);
>> + *b++ = RCS_TIMESTAMP;
>> + b = fill_relocation(b, &relocs[n_relocs++], obj[0].handle,
>> + 0, b - batch,
>> + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
>> +
>> + *b++ = MI_STORE_REGISTER_MEM | (4 - 2);
>> + *b++ = GEN8_R_PWR_CLK_STATE;
>> + b = fill_relocation(b, &relocs[n_relocs++], obj[0].handle,
>> + 4, b - batch,
>> + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER);
>> +
>> + if (expected_slices != 0 && intel_gen(devid) < 10)
>> + *b++ = MI_SET_PREDICATE | (1 - 1) | MI_SET_PREDICATE_NOOP_NEVER;
>> +
>> + *b++ = MI_BATCH_BUFFER_END;
>> +
>> + gem_munmap(batch, 4096);
>> +
>> + obj[1].relocation_count = n_relocs;
>> + obj[1].relocs_ptr = to_user_pointer(relocs);
>> +
>> + memset(&execbuf, 0, sizeof(execbuf));
>> + execbuf.buffers_ptr = to_user_pointer(obj);
>> + execbuf.buffer_count = ARRAY_SIZE(obj);
>> + i915_execbuffer2_set_context_id(execbuf, context);
> Heh.
>
>> + data = gem_mmap__cpu(drm_fd, obj[0].handle, 0, 4096, PROT_READ | PROT_WRITE);
>> + memset(data, 0, 4096);
> You know it's already zero.
>
>> + gem_munmap(data, 4096);
>> +
>> + gem_execbuf(drm_fd, &execbuf);
>> + gem_sync(drm_fd, obj[0].handle);
>> +
>> + data = gem_mmap__cpu(drm_fd, obj[0].handle, 0, 4096, PROT_READ);
>> +
>> + rpcs = data[1];
>> +
> u32 data[2];
> gem_read(drm_fd, obj[0].handle, 0, data, sizeof(data));
>
> No need for the gem_sync, the mmap__cpu or the missing gem_set_domain.
>
>> + igt_debug("rcs_timestamp=0x%x rpcs=0x%x/0x%x\n", data[0], data[1], ((data[1] & GEN8_RPCS_S_CNT_MASK) >> GEN8_RPCS_S_CNT_SHIFT));
>> +
>> + gem_munmap(data, 4096);
>> +
>> + gem_close(drm_fd, obj[0].handle);
>> + gem_close(drm_fd, obj[1].handle);
>> +
>> + return rpcs;
>> +}
>> +
>> +static uint32_t
>> +read_slice_count(uint32_t context,
>> + uint32_t expected_slice_count)
>> +{
>> + return (read_rpcs_reg(context, expected_slice_count) & GEN8_RPCS_S_CNT_MASK)
>> + >> GEN8_RPCS_S_CNT_SHIFT;
>> +}
>> +
>> +static uint32_t
>> +read_subslice_count(uint32_t context)
>> +{
>> + return (read_rpcs_reg(context, 0) & GEN8_RPCS_SS_CNT_MASK)
>> + >> GEN8_RPCS_SS_CNT_SHIFT;
>> +}
>> +
>> +static bool
>> +kernel_has_per_context_sseu_support(void)
>> +{
>> + struct drm_i915_gem_context_param arg;
>> + struct drm_i915_gem_context_param_sseu sseu;
>> +
>> + memset(&sseu, 0, sizeof(sseu));
>> + sseu.class = 0; /* rcs */
>> + sseu.instance = 0;
>> +
>> + memset(&arg, 0, sizeof(arg));
>> + arg.ctx_id = 0; /* default context */
>> + arg.param = I915_CONTEXT_PARAM_SSEU;
>> + arg.value = (uintptr_t) &sseu;
> arg.value = to_user_pointer(&sseu);
>
>> +
>> + if (igt_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg))
>> + return false;
> __gem_context_get_param
>
>> +
>> + return true;
>> +}
>> +
>> +static bool
>> +platform_has_per_context_sseu_support(void)
>> +{
>> + struct drm_i915_gem_context_param arg;
>> + struct drm_i915_gem_context_param_sseu sseu;
>> + int ret;
>> +
>> + memset(&sseu, 0, sizeof(sseu));
>> + sseu.class = 0; /* rcs */
>> + sseu.instance = 0;
>> +
>> + memset(&arg, 0, sizeof(arg));
>> + arg.ctx_id = 0; /* default context */
>> + arg.param = I915_CONTEXT_PARAM_SSEU;
>> + arg.value = (uintptr_t) &sseu;
>> +
>> + ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
>> + igt_assert(ret == 0 || errno == EINVAL);
>> + if (ret)
>> + return false;
>> +
>> + ret = igt_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM, &arg);
>> + igt_assert(ret == 0 || errno == ENODEV);
>> + if (ret)
>> + return false;
>> +
>> + return true;
>> +}
>> +
>> +static void
>> +context_get_sseu_masks(uint32_t context,
>> + uint32_t *slice_mask,
>> + uint32_t *subslice_mask)
>> +{
>> + struct drm_i915_gem_context_param arg;
>> + struct drm_i915_gem_context_param_sseu sseu;
>> +
>> + memset(&sseu, 0, sizeof(sseu));
>> + sseu.class = 0; /* rcs */
>> + sseu.instance = 0;
>> +
>> + memset(&arg, 0, sizeof(arg));
>> + arg.ctx_id = context;
>> + arg.param = I915_CONTEXT_PARAM_SSEU;
>> + arg.value = (uintptr_t) &sseu;
>> +
>> + do_ioctl(drm_fd, DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM, &arg);
> gem_context_get_param etc
> -Chris
>
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