[igt-dev] [PATCH i-g-t 5/6] lib: Add vebox copy support

[Imre Deak]

Hi Guangyao,

On Thu, Dec 05, 2019 at 05:30:49AM +0200, Bai, Guangyao wrote:
> > [...]
> > +
> > +static void emit_tiling_convert_cmd(struct intel_batchbuffer *batch,
> > +				    drm_intel_bo *input_bo,
> > +				    uint32_t input_tiling,
> > +				    uint32_t input_compression,
> > +				    drm_intel_bo *output_bo,
> > +				    uint32_t output_tiling,
> > +				    uint32_t output_compression)
> > +{
> > +	uint32_t reloc_delta;
> > +	struct vebox_tiling_convert *tc;
> > +	int ret;
> > +
> > +	tc = intel_batchbuffer_subdata_alloc(batch, sizeof(*tc), 8);
> > +
> > +	tc->tc0.cmd_type = 3;
> > +	tc->tc0.pipeline = 2;
> > +	tc->tc0.cmd_opcode = 4;
> > +	tc->tc0.sub_opcode_b = 1;
> > +
> > +	tc->tc0.dw_count = 3;
> > +
> > +	if (input_compression != I915_COMPRESSION_NONE) {
> > +		tc->tc1_2.input_memory_compression_enable = 1;
> > +		tc->tc1_2.input_compression_type =
> > +			input_compression == I915_COMPRESSION_RENDER;
> > +	}
> > +	tc->tc1_2.input_tiled_resource_mode = input_tiling == I915_TILING_Yf;
> > +	reloc_delta = tc->tc1_2_l;
> > +
> > +	igt_assert(input_bo->offset64 == ALIGN(input_bo->offset64, 0x1000));
> > +	tc->tc1_2.input_address = input_bo->offset64 >> 12;
> > +	igt_assert(reloc_delta <= INT32_MAX);
> > +	ret = drm_intel_bo_emit_reloc(batch->bo,
> > +				      intel_batchbuffer_subdata_offset(batch, tc)
> > +
> > +					offsetof(typeof(*tc), tc1_2),
> > +				      input_bo, reloc_delta,
> > +				      0, 0);
> > +	igt_assert(ret == 0);
> > +
> > +	if (output_compression != I915_COMPRESSION_NONE) {
> > +		tc->tc3_4.output_memory_compression_enable = 1;
> > +		tc->tc3_4.output_compression_type =
> > +			output_compression == I915_COMPRESSION_RENDER;
> > +	}
> > +	tc->tc3_4.output_tiled_resource_mode = output_tiling == I915_TILING_Yf;
> > +	reloc_delta = tc->tc3_4_l;
> > +
> > +	igt_assert(output_bo->offset64 == ALIGN(output_bo->offset64, 0x1000));
> 
> The Offset64 you gona to align with 4K?

This check here only makes sure that the main surface base address is
sufficiently aligned for the tiling convert command (which requires only
4K alignment).

The base address for main surfaces that are compressed (either render or
media) is already 64K aligned, see aux_pgtable_find_free_range().

> and for the Aux mapping stride(unit), you are using 4K also? Pls check
> the mapping unit and VA define, it should be both 4K or 64K

The main surface stride is aligned to 4 tiles. Since each tile is 32
pixels wide (for 32bpp formats), the main surface stride in bytes is
aligned to

4 tile * 32 pixel/tile * 4 byte/pixel = 512 byte

(or the tile row is aligned to 4 tile * 4kbyte/tile = 16kbyte).

This means the stride for the CCS AUX surface will be aligned to 64
bytes (as one cache line on the CCS AUX surface maps 4 tiles on the main
surface).

--Imre

> 
> > +	tc->tc3_4.output_address = output_bo->offset64 >> 12;
> > +	igt_assert(reloc_delta <= INT32_MAX);
> > +	ret = drm_intel_bo_emit_reloc(batch->bo,
> > +				      intel_batchbuffer_subdata_offset(batch, tc)
> > +
> > +					offsetof(typeof(*tc), tc3_4),
> > +				      output_bo, reloc_delta,
> > +				      0, I915_GEM_DOMAIN_RENDER);
> > +	igt_assert(ret == 0);
> > +
> > +}
> > +