[igt-dev] [PATCH i-g-t v7 4/5] DEBUG:sub-test to check pc8 after enabling all planes on all pipes.
Anshuman Gupta
anshuman.gupta at intel.com
Tue Jun 4 17:56:00 UTC 2019
B.Specs doesn't specify that how many output can be enabled
in order to attain pc8 state. This is just to check whether
a platform can reach pc8 state with all planes enabled on
all pipes.
Signed-off-by: Anshuman Gupta <anshuman.gupta at intel.com>
---
tests/i915/i915_pm_rpm.c | 204 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 203 insertions(+), 1 deletion(-)
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index 0c9a7890..e2b7e1ab 100644
--- a/tests/i915/i915_pm_rpm.c
+++ b/tests/i915/i915_pm_rpm.c
@@ -95,6 +95,9 @@ enum plane_type {
#define WAIT_EXTRA 4
#define USE_DPMS 8
+#define SIZE_PLANE 256
+#define SIZE_CURSOR 128
+
int drm_fd, msr_fd, pc8_status_fd;
int debugfs;
bool has_runtime_pm, has_pc8, pc8_needs_screen_off;
@@ -131,12 +134,22 @@ const char *pch_ip[SIZE_PCH_IP_ARR] = {
"WIGIG"
};
+typedef struct {
+ float red;
+ float green;
+ float blue;
+} color_t;
+
/* Stuff used when creating FBs and mode setting. */
struct mode_set_data {
drmModeResPtr res;
drmModeConnectorPtr connectors[MAX_CONNECTORS];
drmModePropertyBlobPtr edids[MAX_CONNECTORS];
-
+ drmModeModeInfo *mode;
+ igt_plane_t **plane;
+ struct igt_fb *fb_white;
+ igt_display_t display;
+ igt_output_t *output;
uint32_t devid;
};
@@ -182,6 +195,184 @@ static int modprobe(const char *driver)
{
return igt_kmod_load(driver, NULL);
}
+static void
+create_fb_for_mode_position(struct mode_set_data *data, igt_output_t *output,
+ drmModeModeInfo *mode, color_t *color, int *rect_x,
+ int *rect_y, int *rect_w, int *rect_h,
+ uint64_t tiling, int max_planes)
+{
+ unsigned int fb_id;
+ cairo_t *cr;
+ igt_plane_t *primary;
+
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+
+ igt_skip_on(!igt_display_has_format_mod(&data->display,
+ DRM_FORMAT_XRGB8888,
+ tiling));
+
+ fb_id = igt_create_fb(drm_fd,
+ mode->hdisplay, mode->vdisplay,
+ DRM_FORMAT_XRGB8888,
+ tiling,
+ &data->fb_white[primary->index]);
+ igt_assert(fb_id);
+
+ cr = igt_get_cairo_ctx(drm_fd, &data->fb_white[primary->index]);
+ igt_paint_color(cr, rect_x[0], rect_y[0],
+ mode->hdisplay, mode->vdisplay,
+ color->red, color->green, color->blue);
+
+ for (int i = 0; i < max_planes; i++) {
+ if (data->plane[i]->type == DRM_PLANE_TYPE_PRIMARY)
+ continue;
+ igt_paint_color(cr, rect_x[i], rect_y[i],
+ rect_w[i], rect_h[i], 0.0, 0.0, 0.0);
+ }
+
+ igt_put_cairo_ctx(drm_fd, &data->fb_white[primary->index], cr);
+ }
+
+
+static void
+prepare_planes(struct mode_set_data *data, enum pipe pipe_id, color_t *color,
+ uint64_t tiling, int max_planes, igt_output_t *output)
+{
+ drmModeModeInfo *mode;
+ igt_pipe_t *pipe;
+ igt_plane_t *primary;
+ int *x;
+ int *y;
+ int *size;
+ int i;
+
+ igt_output_set_pipe(output, pipe_id);
+ primary = igt_output_get_plane_type(output, DRM_PLANE_TYPE_PRIMARY);
+ pipe = primary->pipe;
+
+ x = malloc(pipe->n_planes * sizeof(*x));
+ igt_assert_f(x, "Failed to allocate %ld bytes for variable x\n",
+ (long)(pipe->n_planes * sizeof(*x)));
+ y = malloc(pipe->n_planes * sizeof(*y));
+ igt_assert_f(y, "Failed to allocate %ld bytes for variable y\n",
+ (long)(pipe->n_planes * sizeof(*y)));
+ size = malloc(pipe->n_planes * sizeof(*size));
+ igt_assert_f(size, "Failed to allocate %ld bytes for variable size\n",
+ (long)(pipe->n_planes * sizeof(*size)));
+
+ mode = igt_output_get_mode(output);
+
+ /* planes with random positions */
+ x[primary->index] = 0;
+ y[primary->index] = 0;
+ for (i = 0; i < max_planes; i++) {
+ igt_plane_t *plane = igt_output_get_plane(output, i);
+ uint32_t plane_format;
+ uint64_t plane_tiling;
+
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+ continue;
+ else if (plane->type == DRM_PLANE_TYPE_CURSOR)
+ size[i] = SIZE_CURSOR;
+ else
+ size[i] = SIZE_PLANE;
+
+ x[i] = rand() % (mode->hdisplay - size[i]);
+ y[i] = rand() % (mode->vdisplay - size[i]);
+
+ data->plane[i] = plane;
+
+ plane_format = data->plane[i]->type == DRM_PLANE_TYPE_CURSOR ?
+ DRM_FORMAT_ARGB8888 : DRM_FORMAT_XRGB8888;
+ plane_tiling = data->plane[i]->type == DRM_PLANE_TYPE_CURSOR ?
+ LOCAL_DRM_FORMAT_MOD_NONE : tiling;
+
+ igt_skip_on(!igt_plane_has_format_mod(plane, plane_format,
+ plane_tiling));
+
+ igt_create_color_fb(drm_fd,
+ size[i], size[i],
+ plane_format,
+ plane_tiling,
+ color->red, color->green, color->blue,
+ &data->fb_white[i]);
+
+ igt_plane_set_position(data->plane[i], x[i], y[i]);
+ igt_plane_set_fb(data->plane[i], &data->fb_white[i]);
+ }
+
+ /* primary plane */
+ data->plane[primary->index] = primary;
+ create_fb_for_mode_position(data, output, mode, color, x, y,
+ size, size, tiling, max_planes);
+ igt_plane_set_fb(data->plane[primary->index],
+ &data->fb_white[primary->index]);
+}
+
+static void setup_output(struct mode_set_data *data)
+{
+ igt_display_t *display = &data->display;
+ igt_output_t *output;
+ igt_plane_t *primary;
+ enum pipe pipe;
+ color_t white = { 1.0f, 1.0f, 1.0f };
+
+ for_each_pipe(display, pipe) {
+ int n_planes = data->display.pipes[pipe].n_planes;
+
+ data->plane = calloc(n_planes, sizeof(*data->plane));
+ igt_assert_f(data->plane != NULL,
+ "Failed to allocate memory for planes\n");
+ data->fb_white = calloc(n_planes, sizeof(struct igt_fb));
+ igt_assert_f(data->fb_white != NULL,
+ "Failed to allocate memory for FBs\n");
+ output = igt_get_single_output_for_pipe(&data->display, pipe);
+ igt_require(output);
+ prepare_planes(data, pipe, &white,
+ LOCAL_DRM_FORMAT_MOD_NONE, n_planes, output);
+ igt_display_commit(&data->display);
+ }
+ return;
+}
+
+static void display_init(struct mode_set_data *data)
+{
+ igt_display_require(&data->display, drm_fd);
+ setup_output(data);
+}
+
+static void display_fini(struct mode_set_data *data)
+{
+ igt_display_fini(&data->display);
+}
+
+static void cleanup(struct mode_set_data *data)
+{
+ enum pipe pipe;
+
+ for_each_pipe(&data->display, pipe) {
+ int n_planes = data->display.pipes[pipe].n_planes;
+
+ for (int i = 0; i < n_planes; i++) {
+ igt_plane_t *plane = data->plane[i];
+
+ if (!plane)
+ continue;
+
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY)
+ continue;
+
+ igt_plane_set_fb(plane, NULL);
+ data->plane[i] = NULL;
+ }
+ }
+
+ free(data->plane);
+ data->plane = NULL;
+ igt_remove_fb(drm_fd, data->fb_white);
+ free(data->fb_white);
+ display_fini(data);
+}
/* If the read fails, then the machine doesn't support PC8+ residencies. */
static bool supports_pc8_plus_residencies(void)
@@ -1015,6 +1206,15 @@ static void pc8_residency_subtest(void)
}
}
+static void pc8_residency_subtest_all_pipes_all_plain(void)
+{
+ display_init(&ms_data);
+ igt_assert_f(pc8_plus_residency_changed(10),
+ "Machine is not reaching PC8+ states "
+ "with all pipes and planes enabled.\n");
+ cleanup(&ms_data);
+}
+
static void modeset_subtest(enum screen_type type, int rounds, int wait_flags)
{
int i;
@@ -2244,6 +2444,8 @@ int main(int argc, char *argv[])
i2c_subtest();
igt_subtest("pc8-residency")
pc8_residency_subtest();
+ igt_subtest("pc8-residency-all-pipes-planes")
+ pc8_residency_subtest_all_pipes_all_plain();
igt_subtest("debugfs-read")
debugfs_read_subtest();
igt_subtest("debugfs-forcewake-user")
--
2.21.0
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