[igt-dev] [RFC v2 28/43] tests/i915/gem_mocs_settings: use the gem_engine_topology library
Ramalingam C
ramalingam.c at intel.com
Fri Jun 21 10:03:30 UTC 2019
Replace the legacy for_each_engine* defines with the ones
implemented in the gem_engine_topology library.
Signed-off-by: Ramalingam C <ramalingam.c at intel.com>
---
tests/i915/gem_mocs_settings.c | 54 +++++++++++++++-------------------
1 file changed, 23 insertions(+), 31 deletions(-)
diff --git a/tests/i915/gem_mocs_settings.c b/tests/i915/gem_mocs_settings.c
index 1a311b8c065b..d5cedfc478c1 100644
--- a/tests/i915/gem_mocs_settings.c
+++ b/tests/i915/gem_mocs_settings.c
@@ -213,7 +213,7 @@ static void do_read_registers(int fd,
uint32_t dst_handle,
uint32_t reg_base,
uint32_t size,
- uint32_t engine_id)
+ const struct intel_execution_engine2 *engine)
{
struct drm_i915_gem_execbuffer2 execbuf;
struct drm_i915_gem_exec_object2 obj[2];
@@ -236,7 +236,7 @@ static void do_read_registers(int fd,
execbuf.batch_len =
create_read_batch(reloc, batch, dst_handle, size, reg_base);
i915_execbuffer2_set_context_id(execbuf, ctx_id);
- execbuf.flags = I915_EXEC_SECURE | engine_id;
+ execbuf.flags = I915_EXEC_SECURE | engine->flags;
gem_write(fd, handle, 0, batch, execbuf.batch_len);
gem_execbuf(fd, &execbuf);
@@ -270,7 +270,7 @@ static void write_registers(int fd,
uint32_t reg_base,
const uint32_t *values,
uint32_t size,
- uint32_t engine_id,
+ const struct intel_execution_engine2 *engine,
bool privileged)
{
struct drm_i915_gem_exec_object2 obj;
@@ -288,9 +288,9 @@ static void write_registers(int fd,
execbuf.batch_len = create_write_batch(batch, values, size, reg_base);
i915_execbuffer2_set_context_id(execbuf, ctx_id);
if (privileged)
- execbuf.flags = I915_EXEC_SECURE | engine_id;
+ execbuf.flags = I915_EXEC_SECURE | engine->flags;
else
- execbuf.flags = engine_id;
+ execbuf.flags = engine->flags;
gem_write(fd, handle, 0, batch, execbuf.batch_len);
gem_execbuf(fd, &execbuf);
@@ -298,11 +298,11 @@ static void write_registers(int fd,
}
static void check_control_registers(int fd,
- unsigned engine,
+ const struct intel_execution_engine2 *engine,
uint32_t ctx_id,
bool dirty)
{
- const uint32_t reg_base = get_engine_base(engine);
+ const uint32_t reg_base = get_engine_base(engine->flags);
uint32_t dst_handle = gem_create(fd, 4096);
uint32_t *read_regs;
struct mocs_table table;
@@ -331,7 +331,7 @@ static void check_control_registers(int fd,
}
static void check_l3cc_registers(int fd,
- unsigned engine,
+ const struct intel_execution_engine2 *engine,
uint32_t ctx_id,
bool dirty)
{
@@ -408,17 +408,17 @@ static void rc6_wait(int i915)
}
static void check_mocs_values(int fd,
- unsigned engine, uint32_t ctx_id,
+ const struct intel_execution_engine2 *engine, uint32_t ctx_id,
bool dirty)
{
check_control_registers(fd, engine, ctx_id, dirty);
- if (engine == I915_EXEC_RENDER)
+ if (engine->class == I915_ENGINE_CLASS_RENDER)
check_l3cc_registers(fd, engine, ctx_id, dirty);
}
static void write_dirty_mocs(int fd,
- unsigned engine, uint32_t ctx_id,
+ const struct intel_execution_engine2 *engine, uint32_t ctx_id,
bool privileged)
{
int num_of_mocs_entries;
@@ -428,17 +428,17 @@ static void write_dirty_mocs(int fd,
else
num_of_mocs_entries = GEN9_NUM_MOCS_ENTRIES;
- write_registers(fd, ctx_id, get_engine_base(engine),
+ write_registers(fd, ctx_id, get_engine_base(engine->flags),
write_values, num_of_mocs_entries,
engine, privileged);
- if (engine == I915_EXEC_RENDER)
+ if (engine->class == I915_ENGINE_CLASS_RENDER)
write_registers(fd, ctx_id, GEN9_LNCFCMOCS0,
write_values, num_of_mocs_entries/2,
engine, privileged);
}
-static void run_test(int fd, unsigned engine, unsigned flags, unsigned mode)
+static void run_test(int fd, const struct intel_execution_engine2 *engine, unsigned flags, unsigned mode)
{
uint32_t ctx_id = 0;
uint32_t ctx_clean_id;
@@ -451,10 +451,10 @@ static void run_test(int fd, unsigned engine, unsigned flags, unsigned mode)
if (flags & MOCS_DIRTY_VALUES)
igt_skip_on(intel_gen(intel_get_drm_devid(fd)) >= 11);
- gem_require_ring(fd, engine);
+ gem_require_ring(fd, engine->flags);
/* Skip if we don't know where the registers are for this engine */
- igt_require(get_engine_base(engine));
+ igt_require(get_engine_base(engine->flags));
if (flags & MOCS_NON_DEFAULT_CTX)
ctx_id = gem_context_create(fd);
@@ -491,7 +491,7 @@ static void run_test(int fd, unsigned engine, unsigned flags, unsigned mode)
gem_context_destroy(fd, ctx_id);
}
-static void isolation_test(int fd, unsigned engine)
+static void isolation_test(int fd, const struct intel_execution_engine2 *engine)
{
uint32_t ctx[2] = { gem_context_create(fd), gem_context_create(fd) };
@@ -505,7 +505,7 @@ static void isolation_test(int fd, unsigned engine)
igt_main
{
- const struct intel_execution_engine *e;
+ const struct intel_execution_engine2 *e;
struct mocs_table table;
int fd = -1;
@@ -516,15 +516,7 @@ igt_main
igt_require(get_mocs_settings(fd, &table, false));
}
- for (e = intel_execution_engines; e->name; e++) {
- /* We don't know which engine will be assigned to us if we're
- * using plain I915_EXEC_BSD, I915_EXEC_DEFAULT is just
- * duplicating render
- */
- if ((e->exec_id == I915_EXEC_BSD && !e->flags) ||
- e->exec_id == I915_EXEC_DEFAULT)
- continue;
-
+ __for_each_static_engine(e) {
for (unsigned mode = NONE; mode < MAX_MOCS_TEST_MODES; mode++) {
igt_subtest_group {
igt_hang_t hang = {};
@@ -542,7 +534,7 @@ igt_main
* Let's also limit testing values on non-default
* contexts to render-only.
*/
- if (flags && e->exec_id != I915_EXEC_RENDER)
+ if (flags && e->class != I915_ENGINE_CLASS_RENDER)
continue;
igt_subtest_f("mocs-%s%s%s-%s",
@@ -553,7 +545,7 @@ igt_main
if (flags & (MOCS_NON_DEFAULT_CTX | MOCS_DIRTY_VALUES))
gem_require_contexts(fd);
- run_test(fd, e->exec_id | e->flags, flags, mode);
+ run_test(fd, e, flags, mode);
}
}
@@ -565,10 +557,10 @@ igt_main
}
igt_subtest_f("mocs-isolation-%s", e->name) {
- gem_require_ring(fd, e->exec_id | e->flags);
+ gem_require_ring(fd, e->flags);
gem_require_contexts(fd);
- isolation_test(fd, e->exec_id | e->flags);
+ isolation_test(fd, e);
}
}
--
2.19.1
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