[igt-dev] [PATCH v14 4/5] lib/i915: add gem_engine_topology library and for_each loop definition
Andi Shyti
andi.shyti at intel.com
Thu Mar 21 01:00:14 UTC 2019
The gem_engine_topology library is a set of functions that
interface with the query and getparam/setparam ioctls.
The library's access point is the 'intel_init_engine_list()'
function that, everytime is called, generates the list of active
engines and returns them in a 'struct intel_engine_data'. The
structure contains only the engines that are actively present in
the GPU.
The function can work in both the cases that the query and
getparam ioctls are implemented or not by the running kernel. In
case they are implemented, a query is made to the driver to fetch
the list of active engines. In case they are not implemented, the
list is taken from the 'intel_execution_engines2' array and
stored only after checking their presence.
Extend the 'for_each_engine_class_instance' so that it can loop
using the new 'intel_init_engine_list()'.
Update accordingly tests/perf_pmu.c, that uses the
'for_each_engine_class_instance()' loop.
Signed-off-by: Andi Shyti <andi.shyti at intel.com>
---
lib/Makefile.sources | 2 +
lib/i915/gem_engine_topology.c | 184 +++++++++++++++++++++++++++++++++
lib/i915/gem_engine_topology.h | 38 +++++++
lib/igt_gt.h | 10 +-
lib/meson.build | 1 +
tests/perf_pmu.c | 8 +-
6 files changed, 236 insertions(+), 7 deletions(-)
create mode 100644 lib/i915/gem_engine_topology.c
create mode 100644 lib/i915/gem_engine_topology.h
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index cf2720981707..757bd7a17ebe 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -13,6 +13,8 @@ lib_source_list = \
i915/gem_ring.c \
i915/gem_mman.c \
i915/gem_mman.h \
+ i915/gem_engine_topology.c \
+ i915/gem_engine_topology.h \
i915_3d.h \
i915_reg.h \
i915_pciids.h \
diff --git a/lib/i915/gem_engine_topology.c b/lib/i915/gem_engine_topology.c
new file mode 100644
index 000000000000..791af8777956
--- /dev/null
+++ b/lib/i915/gem_engine_topology.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+
+#include "i915/gem_engine_topology.h"
+
+#define SIZEOF_CTX_PARAM offsetof(struct i915_context_param_engines, \
+ class_instance[I915_EXEC_RING_MASK + 1])
+#define SIZEOF_QUERY offsetof(struct drm_i915_query_engine_info, \
+ engines[I915_EXEC_RING_MASK + 1])
+
+static int __gem_query(int fd, struct drm_i915_query *q)
+{
+ int err = 0;
+
+ if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+ err = -errno;
+
+ errno = 0;
+ return err;
+}
+
+static void gem_query(int fd, struct drm_i915_query *q)
+{
+ igt_assert_eq(__gem_query(fd, q), 0);
+}
+
+static void query_engines(int fd,
+ struct drm_i915_query_engine_info *query_engines)
+{
+ struct drm_i915_query_item item = { };
+ struct drm_i915_query query = { };
+
+ item.query_id = DRM_I915_QUERY_ENGINE_INFO;
+ query.items_ptr = to_user_pointer(&item);
+ query.num_items = 1;
+ item.length = SIZEOF_QUERY;
+
+ item.data_ptr = to_user_pointer(query_engines);
+
+ gem_query(fd, &query);
+}
+
+static void ctx_map_engines(int fd, struct intel_engine_data *ed,
+ struct drm_i915_gem_context_param *ctx_param)
+{
+ struct i915_context_param_engines *ctx_engine =
+ (struct i915_context_param_engines*) ctx_param->value;
+ int i = 0;
+
+ for (typeof(ctx_engine->class_instance[0]) *p =
+ &ctx_engine->class_instance[0];
+ i < ed->nengines; i++, p++) {
+ p->engine_class = ed->engines[i].class;
+ p->engine_instance = ed->engines[i].instance;
+ }
+
+ ctx_param->size = offsetof(typeof(*ctx_engine), class_instance[i]);
+
+ gem_context_set_param(fd, ctx_param);
+}
+
+static void init_engine(struct intel_execution_engine2 *e2, const char *name,
+ uint16_t class, uint16_t instance, uint8_t flags)
+{
+ static const char *unk_name = "unk";
+
+ e2->class = class;
+ e2->instance = instance;
+ e2->flags = flags;
+
+ if (name) {
+ e2->name = name;
+ } else {
+ const struct intel_execution_engine2 *__e2;
+
+ __for_each_engine_class_instance(__e2)
+ if (__e2->class == class && __e2->instance == instance)
+ break;
+
+ e2->name = __e2->name ? __e2->name : unk_name;
+ }
+}
+
+static void query_engine_list(int fd, struct intel_engine_data *ed)
+{
+ uint8_t query_buffer[SIZEOF_QUERY] = { };
+ struct drm_i915_query_engine_info *query_engine =
+ (struct drm_i915_query_engine_info *) query_buffer;
+ int i;
+
+ query_engines(fd, query_engine);
+
+ for (i = 0; i < query_engine->num_engines; i++)
+ init_engine(&ed->engines[i], NULL,
+ query_engine->engines[i].engine_class,
+ query_engine->engines[i].engine_instance, i);
+
+ ed->nengines = query_engine->num_engines;
+}
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id)
+{
+ struct intel_engine_data engine_data;
+ uint8_t buff[SIZEOF_CTX_PARAM] = { };
+
+ struct i915_context_param_engines *engines =
+ (struct i915_context_param_engines *) buff;
+
+ struct drm_i915_gem_context_param param = {
+ .param = I915_CONTEXT_PARAM_ENGINES,
+ .ctx_id = ctx_id,
+ .size = SIZEOF_CTX_PARAM,
+ .value = to_user_pointer(engines),
+ };
+
+ int i;
+
+ if (__gem_context_get_param(fd, ¶m)) {
+ /* if kernel does not support engine/context mapping */
+ const struct intel_execution_engine2 *e2;
+
+ igt_debug("using pre-allocated engine list\n");
+
+ __for_each_engine_class_instance(e2) {
+ uint64_t flags;
+
+ if (!gem_has_engine(fd, e2->class, e2->instance))
+ continue;
+
+ flags = gem_class_instance_to_eb_flags(fd, e2->class,
+ e2->instance);
+
+ init_engine(&engine_data.engines[engine_data.nengines],
+ e2->name, e2->class, e2->instance, flags);
+
+ engine_data.nengines++;
+ }
+
+ } else if (!param.size) {
+ /* else if context doesn't have mapped engines */
+ query_engine_list(fd, &engine_data);
+ ctx_map_engines(fd, &engine_data, ¶m);
+
+ } else {
+ /* context has a list of mapped engines */
+
+ uint8_t nengines = (param.size -
+ sizeof(struct i915_context_param_engines)) /
+ sizeof(engines->class_instance[0]);
+
+ for (i = 0; i < nengines; i++)
+ init_engine(&engine_data.engines[i], NULL,
+ engines->class_instance[i].engine_class,
+ engines->class_instance[i].engine_instance,
+ i);
+
+ engine_data.nengines = i;
+ }
+
+ return engine_data;
+}
diff --git a/lib/i915/gem_engine_topology.h b/lib/i915/gem_engine_topology.h
new file mode 100644
index 000000000000..31fa3dcaa48c
--- /dev/null
+++ b/lib/i915/gem_engine_topology.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef GEM_ENGINE_TOPOLOGY_H
+#define GEM_ENGINE_TOPOLOGY_H
+
+#include "i915_drm.h"
+#include "igt_gt.h"
+
+struct intel_engine_data {
+ uint32_t nengines;
+ uint32_t n;
+ struct intel_execution_engine2 engines[I915_EXEC_RING_MASK + 1];
+};
+
+struct intel_engine_data intel_init_engine_list(int fd, uint32_t ctx_id);
+
+#endif /* GEM_ENGINE_TOPOLOGY_H */
diff --git a/lib/igt_gt.h b/lib/igt_gt.h
index 475c0b3c3cc6..84ea4af5392d 100644
--- a/lib/igt_gt.h
+++ b/lib/igt_gt.h
@@ -95,6 +95,7 @@ extern const struct intel_execution_engine2 {
const char *name;
int class;
int instance;
+ uint64_t flags;
} intel_execution_engines2[];
unsigned int
@@ -117,8 +118,11 @@ void gem_require_engine(int gem_fd,
#define __for_each_engine_class_instance(e__) \
for ((e__) = intel_execution_engines2; (e__)->name; (e__)++)
-#define for_each_engine_class_instance(fd__, e__) \
- for ((e__) = intel_execution_engines2; (e__)->name; (e__)++) \
- for_if (gem_has_engine((fd__), (e__)->class, (e__)->instance))
+#include "i915/gem_engine_topology.h"
+
+#define for_each_engine_class_instance(fd__, ctx__, e__) \
+ for (struct intel_engine_data i__ = intel_init_engine_list(fd__, ctx__); \
+ ((e__) = (i__.n < i__.nengines) ? &i__.engines[i__.n] : NULL); \
+ i__.n++)
#endif /* IGT_GT_H */
diff --git a/lib/meson.build b/lib/meson.build
index 0eb5585d72b9..3cc52f97c8bf 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -5,6 +5,7 @@ lib_sources = [
'i915/gem_submission.c',
'i915/gem_ring.c',
'i915/gem_mman.c',
+ 'i915/gem_engine_topology.c',
'igt_color_encoding.c',
'igt_debugfs.c',
'igt_device.c',
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index 4f552bc2ae28..c9c63405cdde 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -434,7 +434,7 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
i = 0;
fd[0] = -1;
- for_each_engine_class_instance(gem_fd, e_) {
+ for_each_engine_class_instance(gem_fd, 0, e_) {
if (e == e_)
busy_idx = i;
@@ -497,7 +497,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
unsigned int idle_idx, i;
i = 0;
- for_each_engine_class_instance(gem_fd, e_) {
+ for_each_engine_class_instance(gem_fd, 0, e_) {
if (e == e_)
idle_idx = i;
else if (spin)
@@ -554,7 +554,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
unsigned int i;
i = 0;
- for_each_engine_class_instance(gem_fd, e) {
+ for_each_engine_class_instance(gem_fd, 0, e) {
if (spin)
__submit_spin_batch(gem_fd, spin, e, 64);
else
@@ -1683,7 +1683,7 @@ igt_main
igt_require_gem(fd);
igt_require(i915_type_id() > 0);
- for_each_engine_class_instance(fd, e)
+ for_each_engine_class_instance(fd, 0, e)
num_engines++;
}
--
2.20.1
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