[igt-dev] [PATCH i-g-t v5 4/5] lib/intel_mmio: remove igt_global_mmio and move it to mmio_data
Jani Nikula
jani.nikula at linux.intel.com
Thu May 9 13:52:34 UTC 2019
On Thu, 09 May 2019, Daniel Mrzyglod <daniel.t.mrzyglod at intel.com> wrote:
> this patch remove need for igt_global_mmio from library space.
> The reason that it was moved is the idea to support multiple
> devices at once.
>
> Signed-off-by: Daniel Mrzyglod <daniel.t.mrzyglod at intel.com>
> ---
> benchmarks/gem_latency.c | 5 +-
> benchmarks/gem_wsim.c | 6 +-
> lib/intel_io.h | 78 +++++++++++++--------
> lib/intel_iosf.c | 74 +++++++++++---------
> lib/intel_mmio.c | 123 ++++++++++++++++------------------
> tests/i915/gem_exec_latency.c | 7 +-
> tests/i915/gem_exec_parse.c | 14 ++--
> tests/i915/i915_pm_lpsp.c | 7 +-
> tools/intel_audio_dump.c | 7 +-
> tools/intel_backlight.c | 5 +-
> tools/intel_display_poller.c | 7 +-
> tools/intel_forcewaked.c | 14 ++--
> tools/intel_gpu_time.c | 5 +-
> tools/intel_infoframes.c | 7 +-
> tools/intel_l3_parity.c | 14 ++--
> tools/intel_lid.c | 6 +-
> tools/intel_panel_fitter.c | 7 +-
> tools/intel_perf_counters.c | 17 +++--
> tools/intel_reg.c | 31 ++++++---
> tools/intel_reg_checker.c | 6 +-
> tools/intel_watermark.c | 44 +++++++-----
> 21 files changed, 292 insertions(+), 192 deletions(-)
>
> diff --git a/benchmarks/gem_latency.c b/benchmarks/gem_latency.c
> index c3fc4bf0..bcaaecef 100644
> --- a/benchmarks/gem_latency.c
> +++ b/benchmarks/gem_latency.c
> @@ -55,6 +55,8 @@
> static int done;
> static int fd;
> static volatile uint32_t *timestamp_reg;
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> #define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x)
> #define REG_OFFSET(x) ((volatile char *)(x) - (volatile char *)igt_global_mmio)
> @@ -456,7 +458,8 @@ static int run(int seconds,
> if (gen < 6)
> return IGT_EXIT_SKIP; /* Needs BCS timestamp */
>
> - intel_register_access_init(intel_get_pci_device(), false, fd);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> if (gen == 6)
> timestamp_reg = REG(RCS_TIMESTAMP);
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index afb9644d..86af58cb 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -206,6 +206,9 @@ struct workload
> } busy_balancer;
> };
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
> +
> static const unsigned int nop_calibration_us = 1000;
> static unsigned long nop_calibration;
>
> @@ -2223,7 +2226,8 @@ static void init_clocks(void)
> uint32_t rcs_start, rcs_end;
> double overhead, t;
>
> - intel_register_access_init(intel_get_pci_device(), false, fd);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, fd);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> if (verbose <= 1)
> return;
> diff --git a/lib/intel_io.h b/lib/intel_io.h
> index 0674b42c..5f9ea724 100644
> --- a/lib/intel_io.h
> +++ b/lib/intel_io.h
> @@ -30,17 +30,41 @@
>
> #include <stdint.h>
> #include <pciaccess.h>
> +#include <stdbool.h>
>
> /* register access helpers from intel_mmio.c */
> -extern void *igt_global_mmio;
> -void intel_mmio_use_pci_bar(struct pci_device *pci_dev);
> -void intel_mmio_use_dump_file(char *file);
> +struct intel_register_range {
> + uint32_t base;
> + uint32_t size;
> + uint32_t flags;
> +};
> +
> +struct intel_register_map {
> + struct intel_register_range *map;
> + uint32_t top;
> + uint32_t alignment_mask;
> +};
> +
> +struct _mmio_data {
> + int inited;
> + bool safe;
> + uint32_t i915_devid;
> + struct intel_register_map map;
> + int key;
> + void *igt_mmio;
> +};
> +
> +void intel_mmio_use_pci_bar(struct _mmio_data *mmio_data,
> + struct pci_device *pci_dev);
> +void intel_mmio_use_dump_file(struct _mmio_data *mmio_data, char *file);
>
> -int intel_register_access_init(struct pci_device *pci_dev, int safe, int fd);
> -void intel_register_access_fini(void);
> -uint32_t intel_register_read(uint32_t reg);
> -void intel_register_write(uint32_t reg, uint32_t val);
> -int intel_register_access_needs_fakewake(void);
> +int intel_register_access_init(struct _mmio_data *mmio_data,
> + struct pci_device *pci_dev, int safe, int fd);
> +void intel_register_access_fini(struct _mmio_data *mmio_data);
> +uint32_t intel_register_read(struct _mmio_data *mmio_data, uint32_t reg);
> +void intel_register_write(struct _mmio_data *mmio_data, uint32_t reg,
> + uint32_t val);
> +int intel_register_access_needs_fakewake(struct _mmio_data *mmio_data);
>
> uint32_t INREG(void *igt_mmio, uint32_t reg);
> uint16_t INREG16(void *igt_mmio, uint32_t reg);
> @@ -50,17 +74,24 @@ void OUTREG16(void *igt_mmio, uint32_t reg, uint16_t val);
> void OUTREG8(void *igt_mmio, uint32_t reg, uint8_t val);
>
> /* sideband access functions from intel_iosf.c */
> -uint32_t intel_dpio_reg_read(uint32_t reg, int phy);
> -void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy);
> -uint32_t intel_flisdsi_reg_read(uint32_t reg);
> -void intel_flisdsi_reg_write(uint32_t reg, uint32_t val);
> -uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg);
> -void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val);
> +uint32_t intel_dpio_reg_read(struct _mmio_data *mmio_data, uint32_t reg,
> + int phy);
> +void intel_dpio_reg_write(struct _mmio_data *mmio_data, uint32_t reg,
> + uint32_t val, int phy);
> +uint32_t intel_flisdsi_reg_read(struct _mmio_data *mmio_data, uint32_t reg);
> +void intel_flisdsi_reg_write(struct _mmio_data *mmio_data, uint32_t reg,
> + uint32_t val);
> +uint32_t intel_iosf_sb_read(struct _mmio_data *mmio_data, uint32_t port,
> + uint32_t reg);
> +void intel_iosf_sb_write(struct _mmio_data *mmio_data, uint32_t port,
> + uint32_t reg, uint32_t val);
>
> -int intel_punit_read(uint32_t addr, uint32_t *val);
> -int intel_punit_write(uint32_t addr, uint32_t val);
> -int intel_nc_read(uint32_t addr, uint32_t *val);
> -int intel_nc_write(uint32_t addr, uint32_t val);
> +int intel_punit_read(struct _mmio_data *mmio_data, uint32_t addr,
> + uint32_t *val);
> +int intel_punit_write(struct _mmio_data *mmio_data, uint32_t addr,
> + uint32_t val);
> +int intel_nc_read(struct _mmio_data *mmio_data, uint32_t addr, uint32_t *val);
> +int intel_nc_write(struct _mmio_data *mmio_data, uint32_t addr, uint32_t val);
>
> /* register maps from intel_reg_map.c */
> #ifndef __GTK_DOC_IGNORE__
> @@ -71,17 +102,8 @@ int intel_nc_write(uint32_t addr, uint32_t val);
> #define INTEL_RANGE_RW (INTEL_RANGE_READ | INTEL_RANGE_WRITE)
> #define INTEL_RANGE_END (1<<31)
>
> -struct intel_register_range {
> - uint32_t base;
> - uint32_t size;
> - uint32_t flags;
> -};
>
> -struct intel_register_map {
> - struct intel_register_range *map;
> - uint32_t top;
> - uint32_t alignment_mask;
> -};
> +//static struct _mmio_data mmio_data;
> struct intel_register_map intel_get_register_map(uint32_t devid);
> struct intel_register_range *intel_get_register_range(struct intel_register_map map, uint32_t offset, uint32_t mode);
> #endif /* __GTK_DOC_IGNORE__ */
> diff --git a/lib/intel_iosf.c b/lib/intel_iosf.c
> index 3b5a1370..2e23dd29 100644
> --- a/lib/intel_iosf.c
> +++ b/lib/intel_iosf.c
> @@ -19,8 +19,8 @@
> /* Private register write, double-word addressing, non-posted */
> #define SB_CRWRDA_NP 0x07
>
> -static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
> - uint32_t *val)
> +static int vlv_sideband_rw(struct _mmio_data *mmio_data, uint32_t port,
> + uint8_t opcode, uint32_t addr, uint32_t *val)
> {
> int timeout = 0;
> uint32_t cmd, devfn, be, bar;
> @@ -34,22 +34,24 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
> (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
> (bar << IOSF_BAR_SHIFT);
>
> - if (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
> + if (intel_register_read(mmio_data, VLV_IOSF_DOORBELL_REQ) &
> + IOSF_SB_BUSY) {
> igt_warn("warning: pcode (%s) mailbox access failed\n", is_read ? "read" : "write");
> return -EAGAIN;
> }
>
> - intel_register_write(VLV_IOSF_ADDR, addr);
> + intel_register_write(mmio_data, VLV_IOSF_ADDR, addr);
> if (!is_read)
> - intel_register_write(VLV_IOSF_DATA, *val);
> + intel_register_write(mmio_data, VLV_IOSF_DATA, *val);
>
> - intel_register_write(VLV_IOSF_DOORBELL_REQ, cmd);
> + intel_register_write(mmio_data, VLV_IOSF_DOORBELL_REQ, cmd);
>
> do {
> usleep(1);
> timeout++;
> - } while (intel_register_read(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY &&
> - timeout < TIMEOUT_US);
> + } while (intel_register_read(mmio_data->igt_mmio,
> + VLV_IOSF_DOORBELL_REQ) &
> + IOSF_SB_BUSY && timeout < TIMEOUT_US);
>
> if (timeout >= TIMEOUT_US) {
> igt_warn("timeout waiting for pcode %s (%d) to finish\n", is_read ? "read" : "write", addr);
> @@ -57,8 +59,8 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
> }
>
> if (is_read)
> - *val = intel_register_read(VLV_IOSF_DATA);
> - intel_register_write(VLV_IOSF_DATA, 0);
> + *val = intel_register_read(mmio_data->igt_mmio, VLV_IOSF_DATA);
> + intel_register_write(mmio_data->igt_mmio, VLV_IOSF_DATA, 0);
>
> return 0;
> }
> @@ -73,9 +75,10 @@ static int vlv_sideband_rw(uint32_t port, uint8_t opcode, uint32_t addr,
> * Returns:
> * 0 when the register access succeeded, negative errno code on failure.
> */
> -int intel_punit_read(uint32_t addr, uint32_t *val)
> +int intel_punit_read(struct _mmio_data *mmio_data, uint32_t addr, uint32_t *val)
> {
> - return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr, val);
> + return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRRDDA_NP, addr,
> + val);
> }
>
> /**
> @@ -88,9 +91,10 @@ int intel_punit_read(uint32_t addr, uint32_t *val)
> * Returns:
> * 0 when the register access succeeded, negative errno code on failure.
> */
> -int intel_punit_write(uint32_t addr, uint32_t val)
> +int intel_punit_write(struct _mmio_data *mmio_data, uint32_t addr, uint32_t val)
> {
> - return vlv_sideband_rw(IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr, &val);
> + return vlv_sideband_rw(mmio_data, IOSF_PORT_PUNIT, SB_CRWRDA_NP, addr,
> + &val);
> }
>
> /**
> @@ -103,9 +107,10 @@ int intel_punit_write(uint32_t addr, uint32_t val)
> * Returns:
> * 0 when the register access succeeded, negative errno code on failure.
> */
> -int intel_nc_read(uint32_t addr, uint32_t *val)
> +int intel_nc_read(struct _mmio_data *mmio_data, uint32_t addr, uint32_t *val)
> {
> - return vlv_sideband_rw(IOSF_PORT_NC, SB_CRRDDA_NP, addr, val);
> + return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRRDDA_NP, addr,
> + val);
> }
>
> /**
> @@ -118,9 +123,10 @@ int intel_nc_read(uint32_t addr, uint32_t *val)
> * Returns:
> * 0 when the register access succeeded, negative errno code on failure.
> */
> -int intel_nc_write(uint32_t addr, uint32_t val)
> +int intel_nc_write(struct _mmio_data *mmio_data, uint32_t addr, uint32_t val)
> {
> - return vlv_sideband_rw(IOSF_PORT_NC, SB_CRWRDA_NP, addr, &val);
> + return vlv_sideband_rw(mmio_data, IOSF_PORT_NC, SB_CRWRDA_NP, addr,
> + &val);
> }
>
> /**
> @@ -133,14 +139,16 @@ int intel_nc_write(uint32_t addr, uint32_t val)
> * Returns:
> * The value read from the register.
> */
> -uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
> +uint32_t intel_dpio_reg_read(struct _mmio_data *mmio_data, uint32_t reg, int phy)
> {
> uint32_t val;
>
> if (phy == 0)
> - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MRD_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MRD_NP, reg,
> + &val);
> else
> - vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MRD_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MRD_NP, reg,
> + &val);
> return val;
> }
>
> @@ -152,38 +160,40 @@ uint32_t intel_dpio_reg_read(uint32_t reg, int phy)
> *
> * 32-bit write of the register at @offset through the DPIO sideband port.
> */
> -void intel_dpio_reg_write(uint32_t reg, uint32_t val, int phy)
> +void intel_dpio_reg_write(struct _mmio_data *mmio_data, uint32_t reg, uint32_t val, int phy)
> {
> if (phy == 0)
> - vlv_sideband_rw(IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO, SB_MWR_NP, reg, &val);
> else
> - vlv_sideband_rw(IOSF_PORT_DPIO_2, SB_MWR_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, IOSF_PORT_DPIO_2, SB_MWR_NP, reg,
> + &val);
> }
>
> -uint32_t intel_flisdsi_reg_read(uint32_t reg)
> +uint32_t intel_flisdsi_reg_read(struct _mmio_data *mmio_data, uint32_t reg)
> {
> uint32_t val = 0;
>
> - vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, reg, &val);
>
> return val;
> }
>
> -void intel_flisdsi_reg_write(uint32_t reg, uint32_t val)
> +void intel_flisdsi_reg_write(struct _mmio_data *mmio_data, uint32_t reg, uint32_t val)
> {
> - vlv_sideband_rw(IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, IOSF_PORT_FLISDSI, SB_CRWRDA_NP, reg, &val);
> }
>
> -uint32_t intel_iosf_sb_read(uint32_t port, uint32_t reg)
> +uint32_t intel_iosf_sb_read(struct _mmio_data *mmio_data, uint32_t port, uint32_t reg)
> {
> uint32_t val;
>
> - vlv_sideband_rw(port, SB_CRRDDA_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, port, SB_CRRDDA_NP, reg, &val);
>
> return val;
> }
>
> -void intel_iosf_sb_write(uint32_t port, uint32_t reg, uint32_t val)
> +void intel_iosf_sb_write(struct _mmio_data *mmio_data, uint32_t port,
> + uint32_t reg, uint32_t val)
> {
> - vlv_sideband_rw(port, SB_CRWRDA_NP, reg, &val);
> + vlv_sideband_rw(mmio_data, port, SB_CRWRDA_NP, reg, &val);
> }
> diff --git a/lib/intel_mmio.c b/lib/intel_mmio.c
> index d473cd9b..42aff2b7 100644
> --- a/lib/intel_mmio.c
> +++ b/lib/intel_mmio.c
> @@ -65,32 +65,17 @@
>
> #define FAKEKEY 0x2468ace0
>
> -/**
> - * igt_global_mmio:
> - *
> - * Pointer to the register range, initialized using intel_register_access_init()
> - * or intel_mmio_use_dump_file(). It is not recommended to use this directly.
> - */
> -void *igt_global_mmio;
> -
> -static struct _mmio_data {
> - int inited;
> - bool safe;
> - uint32_t i915_devid;
> - struct intel_register_map map;
> - int key;
> -} mmio_data;
> -
> /**
> * intel_mmio_use_dump_file:
> + * @mmio_data: mmio structure for IO operations
> * @file: name of the register dump file to open
> *
> - * Sets up #igt_global_mmio to point at the data contained in @file. This allows
> - * the same code to get reused for dumping and decoding from running hardware as
> - * from register dumps.
> + * Sets also up mmio_data->igt_mmio to point at the data contained
> + * in @file. This allows the same code to get reused for dumping and decoding
> + * from running hardware as from register dumps.
> */
> void
> -intel_mmio_use_dump_file(char *file)
> +intel_mmio_use_dump_file(struct _mmio_data *mmio_data, char *file)
> {
> int fd;
> struct stat st;
> @@ -100,22 +85,23 @@ intel_mmio_use_dump_file(char *file)
> "Couldn't open %s\n", file);
>
> fstat(fd, &st);
> - igt_global_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
> - igt_fail_on_f(igt_global_mmio == MAP_FAILED,
> + mmio_data->igt_mmio = mmap(NULL, st.st_size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
> + igt_fail_on_f(mmio_data->igt_mmio == MAP_FAILED,
> "Couldn't mmap %s\n", file);
> close(fd);
> }
>
> /**
> * intel_mmio_use_pci_bar:
> + * @mmio_data: mmio structure for IO operations
> * @pci_dev: intel gracphis pci device
> *
> - * Sets up #igt_global_mmio to point at the mmio bar.
> + * Fill a mmio_data stucture with igt_mmio to point at the mmio bar.
> *
> * @pci_dev can be obtained from intel_get_pci_device().
> */
> void
> -intel_mmio_use_pci_bar(struct pci_device *pci_dev)
> +intel_mmio_use_pci_bar(struct _mmio_data *mmio_data, struct pci_device *pci_dev)
> {
> uint32_t devid, gen;
> int mmio_bar, mmio_size;
> @@ -139,7 +125,7 @@ intel_mmio_use_pci_bar(struct pci_device *pci_dev)
> pci_dev->regions[mmio_bar].base_addr,
> mmio_size,
> PCI_DEV_MAP_FLAG_WRITABLE,
> - &igt_global_mmio);
> + &mmio_data->igt_mmio);
>
> igt_fail_on_f(error != 0,
> "Couldn't map MMIO region\n");
> @@ -153,6 +139,7 @@ release_forcewake_lock(int fd)
>
> /**
> * intel_register_access_init:
> + * @mmio_data: mmio structure for IO operations
> * @pci_dev: intel graphics pci device
> * @safe: use safe register access tables
> *
> @@ -160,76 +147,79 @@ release_forcewake_lock(int fd)
> * handling and also allows register access to be checked with an explicit
> * whitelist.
> *
> - * It also initializes #igt_global_mmio like intel_mmio_use_pci_bar().
> + * It also initializes mmio_data->igt_mmio like intel_mmio_use_pci_bar().
> *
> * @pci_dev can be obtained from intel_get_pci_device().
> */
> int
> -intel_register_access_init(struct pci_device *pci_dev, int safe, int fd)
> +intel_register_access_init(struct _mmio_data *mmio_data, struct pci_device *pci_dev, int safe, int fd)
> {
> int ret;
>
> /* after old API is deprecated, remove this */
> - if (igt_global_mmio == NULL)
> - intel_mmio_use_pci_bar(pci_dev);
> + if (mmio_data->igt_mmio == NULL)
> + intel_mmio_use_pci_bar(mmio_data, pci_dev);
>
> - igt_assert(igt_global_mmio != NULL);
> + igt_assert(mmio_data->igt_mmio != NULL);
>
> - if (mmio_data.inited)
> + if (mmio_data->inited)
> return -1;
>
> - mmio_data.safe = (safe != 0 &&
> + mmio_data->safe = (safe != 0 &&
> intel_gen(pci_dev->device_id) >= 4) ? true : false;
> - mmio_data.i915_devid = pci_dev->device_id;
> - if (mmio_data.safe)
> - mmio_data.map = intel_get_register_map(mmio_data.i915_devid);
> + mmio_data->i915_devid = pci_dev->device_id;
> + if (mmio_data->safe)
> + mmio_data->map = intel_get_register_map(mmio_data->i915_devid);
>
> /* Find where the forcewake lock is. Forcewake doesn't exist
> * gen < 6, but the debugfs should do the right things for us.
> */
> ret = igt_open_forcewake_handle(fd);
> if (ret == -1)
> - mmio_data.key = FAKEKEY;
> + mmio_data->key = FAKEKEY;
> else
> - mmio_data.key = ret;
> + mmio_data->key = ret;
>
> - mmio_data.inited++;
> + mmio_data->inited++;
> return 0;
> }
>
> static int
> -intel_register_access_needs_wake(void)
> +intel_register_access_needs_wake(struct _mmio_data *mmio_data)
> {
> - return mmio_data.key != FAKEKEY;
> + return mmio_data->key != FAKEKEY;
> }
>
> /**
> * intel_register_access_needs_fakewake:
> + * @mmio_data: mmio structure for IO operations
> *
> * Returns:
> * Non-zero when forcewake initialization failed.
> */
> -int intel_register_access_needs_fakewake(void)
> +int intel_register_access_needs_fakewake(struct _mmio_data *mmio_data)
> {
> - return mmio_data.key == FAKEKEY;
> + return mmio_data->key == FAKEKEY;
> }
>
> /**
> * intel_register_access_fini:
> + * @mmio_data: mmio structure for IO operations
> *
> * Clean up the register access helper initialized with
> * intel_register_access_init().
> */
> void
> -intel_register_access_fini(void)
> +intel_register_access_fini(struct _mmio_data *mmio_data)
> {
> - if (mmio_data.key && intel_register_access_needs_wake())
> - release_forcewake_lock(mmio_data.key);
> - mmio_data.inited--;
> + if (mmio_data->key && intel_register_access_needs_wake(mmio_data))
> + release_forcewake_lock(mmio_data->key);
> + mmio_data->inited--;
> }
>
> /**
> * intel_register_read:
> + * @mmio_data: mmio structure for IO operations
> * @reg: register offset
> *
> * 32-bit read of the register at @offset. This function only works when the new
> @@ -242,20 +232,20 @@ intel_register_access_fini(void)
> * The value read from the register.
> */
> uint32_t
> -intel_register_read(uint32_t reg)
> +intel_register_read(struct _mmio_data *mmio_data, uint32_t reg)
> {
> struct intel_register_range *range;
> uint32_t ret;
>
> - igt_assert(mmio_data.inited);
> + igt_assert(mmio_data->inited);
>
> - if (intel_gen(mmio_data.i915_devid) >= 6)
> - igt_assert(mmio_data.key != -1);
> + if (intel_gen(mmio_data->i915_devid) >= 6)
> + igt_assert(mmio_data->key != -1);
>
> - if (!mmio_data.safe)
> + if (!mmio_data->safe)
> goto read_out;
>
> - range = intel_get_register_range(mmio_data.map,
> + range = intel_get_register_range(mmio_data->map,
> reg,
> INTEL_RANGE_READ);
>
> @@ -266,13 +256,14 @@ intel_register_read(uint32_t reg)
> }
>
> read_out:
> - ret = *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg);
> + ret = *(volatile uint32_t *)((volatile char *)mmio_data->igt_mmio + reg);
> out:
> return ret;
> }
>
> /**
> * intel_register_write:
> + * @mmio_data: mmio structure for IO operations
> * @reg: register offset
> * @val: value to write
> *
> @@ -283,19 +274,19 @@ out:
> * white lists.
> */
> void
> -intel_register_write(uint32_t reg, uint32_t val)
> +intel_register_write(struct _mmio_data *mmio_data, uint32_t reg, uint32_t val)
> {
> struct intel_register_range *range;
>
> - igt_assert(mmio_data.inited);
> + igt_assert(mmio_data->inited);
>
> - if (intel_gen(mmio_data.i915_devid) >= 6)
> - igt_assert(mmio_data.key != -1);
> + if (intel_gen(mmio_data->i915_devid) >= 6)
> + igt_assert(mmio_data->key != -1);
>
> - if (!mmio_data.safe)
> + if (!mmio_data->safe)
> goto write_out;
>
> - range = intel_get_register_range(mmio_data.map,
> + range = intel_get_register_range(mmio_data->map,
> reg,
> INTEL_RANGE_WRITE);
>
> @@ -303,7 +294,7 @@ intel_register_write(uint32_t reg, uint32_t val)
> "Register write blocked for safety ""(*0x%08x = 0x%x)\n", reg, val);
>
> write_out:
> - *(volatile uint32_t *)((volatile char *)igt_global_mmio + reg) = val;
> + *(volatile uint32_t *)((volatile char *)mmio_data->igt_mmio + reg) = val;
> }
>
>
> @@ -315,7 +306,7 @@ write_out:
> * 32-bit read of the register at offset @reg. This function only works when the
> * new register access helper is initialized with intel_register_access_init().
> *
> - * This function directly accesses the #igt_global_mmio without safety checks.
> + * This function directly accesses the igt_mmio without safety checks.
> *
> * Returns:
> * The value read from the register.
> @@ -333,7 +324,7 @@ uint32_t INREG(void *igt_mmio, uint32_t reg)
> * 16-bit read of the register at offset @reg. This function only works when the
> * new register access helper is initialized with intel_register_access_init().
> *
> - * This function directly accesses the #igt_global_mmio without safety checks.
> + * This function directly accesses the igt_mmio without safety checks.
> *
> * Returns:
> * The value read from the register.
> @@ -351,7 +342,7 @@ uint16_t INREG16(void *igt_mmio, uint32_t reg)
> * 8-bit read of the register at offset @reg. This function only works when the
> * new register access helper is initialized with intel_register_access_init().
> *
> - * This function directly accesses the #igt_global_mmio without safety checks.
> + * This function directly accesses the igt_mmio without safety checks.
> *
> * Returns:
> * The value read from the register.
> @@ -371,7 +362,7 @@ uint8_t INREG8(void *igt_mmio, uint32_t reg)
> * when the new register access helper is initialized with
> * intel_register_access_init().
> *
> - * This function directly accesses the #igt_global_mmio without safety checks.
> + * This function directly accesses the igt_mmio without safety checks.
> */
> void OUTREG(void *igt_mmio, uint32_t reg, uint32_t val)
> {
> @@ -387,7 +378,7 @@ void OUTREG(void *igt_mmio, uint32_t reg, uint32_t val)
> * when the new register access helper is initialized with
> * intel_register_access_init().
> *
> - * This function directly accesses the #igt_global_mmio without safety checks.
> + * This function directly accesses the igt_mmio without safety checks.
> */
> void OUTREG16(void *igt_mmio, uint32_t reg, uint16_t val)
> {
> @@ -404,7 +395,7 @@ void OUTREG16(void *igt_mmio, uint32_t reg, uint16_t val)
> * when the new register access helper is initialized with
> * intel_register_access_init().
> *
> - * This function directly accesses the #igt_global_mmio without safety checks.
> + * This function directly accesses the igt_mmio without safety checks.
> */
> void OUTREG8(void *igt_mmio, uint32_t reg, uint8_t val)
> {
> diff --git a/tests/i915/gem_exec_latency.c b/tests/i915/gem_exec_latency.c
> index e56d6278..6379edae 100644
> --- a/tests/i915/gem_exec_latency.c
> +++ b/tests/i915/gem_exec_latency.c
> @@ -62,6 +62,9 @@
> static unsigned int ring_size;
> static double rcs_clock;
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
> +
> static void
> poll_ring(int fd, unsigned ring, const char *name)
> {
> @@ -667,7 +670,9 @@ igt_main
> if (ring_size > 1024)
> ring_size = 1024;
>
> - intel_register_access_init(intel_get_pci_device(), false, device);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), false, device);
> + igt_global_mmio = mmio_data.igt_mmio;
> +
> rcs_clock = clockrate(device, RCS_TIMESTAMP);
> igt_info("RCS timestamp clock: %.0fKHz, %.1fns\n",
> rcs_clock / 1e3, 1e9 / rcs_clock);
> diff --git a/tests/i915/gem_exec_parse.c b/tests/i915/gem_exec_parse.c
> index 62e8d0a5..98b05267 100644
> --- a/tests/i915/gem_exec_parse.c
> +++ b/tests/i915/gem_exec_parse.c
> @@ -58,6 +58,9 @@
>
> static int parser_version;
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
> +
> static int command_parser_version(int fd)
> {
> int version = -1;
> @@ -284,9 +287,9 @@ test_lri(int fd, uint32_t handle, struct test_lri *test)
> test->name, test->reg, test->test_val,
> expected_errno, expect);
>
> - intel_register_write(test->reg, test->init_val);
> + intel_register_write(&mmio_data, test->reg, test->init_val);
>
> - igt_assert_eq_u32((intel_register_read(test->reg) &
> + igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) &
> test->read_mask),
> test->init_val);
>
> @@ -296,7 +299,7 @@ test_lri(int fd, uint32_t handle, struct test_lri *test)
> expected_errno);
> gem_sync(fd, handle);
>
> - igt_assert_eq_u32((intel_register_read(test->reg) &
> + igt_assert_eq_u32((intel_register_read(&mmio_data, test->reg) &
> test->read_mask),
> expect);
> }
> @@ -530,7 +533,8 @@ igt_main
> #undef REG
>
> igt_fixture {
> - intel_register_access_init(intel_get_pci_device(), 0, fd);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, fd);
> + igt_global_mmio = mmio_data.igt_mmio;
> }
>
> for (int i = 0; i < ARRAY_SIZE(lris); i++) {
> @@ -543,7 +547,7 @@ igt_main
> }
>
> igt_fixture {
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
> }
> }
>
> diff --git a/tests/i915/i915_pm_lpsp.c b/tests/i915/i915_pm_lpsp.c
> index f69c88f6..cbbe6a4b 100644
> --- a/tests/i915/i915_pm_lpsp.c
> +++ b/tests/i915/i915_pm_lpsp.c
> @@ -30,6 +30,8 @@
> #include <fcntl.h>
> #include <unistd.h>
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> static bool supports_lpsp(uint32_t devid)
> {
> @@ -210,7 +212,8 @@ igt_main
>
> igt_require(supports_lpsp(devid));
>
> - intel_register_access_init(intel_get_pci_device(), 0, drm_fd);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, drm_fd);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> kmstest_set_vt_graphics_mode();
> }
> @@ -227,7 +230,7 @@ igt_main
> igt_fixture {
> int i;
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
> for (i = 0; i < drm_res->count_connectors; i++)
> drmModeFreeConnector(drm_connectors[i]);
> drmModeFreeResources(drm_res);
> diff --git a/tools/intel_audio_dump.c b/tools/intel_audio_dump.c
> index 678e1d08..119fece1 100644
> --- a/tools/intel_audio_dump.c
> +++ b/tools/intel_audio_dump.c
> @@ -41,6 +41,8 @@ static uint32_t devid;
>
> static int aud_reg_base = 0; /* base address of audio registers */
> static int disp_reg_base = 0; /* base address of display registers */
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> #define IS_HASWELL_PLUS(devid) (IS_HASWELL(devid) || IS_BROADWELL(devid))
>
> @@ -2498,9 +2500,10 @@ int main(int argc, char **argv)
> do_self_tests();
>
> if (argc == 2)
> - intel_mmio_use_dump_file(argv[1]);
> + intel_mmio_use_dump_file(&mmio_data, argv[1]);
> else
> - intel_mmio_use_pci_bar(pci_dev);
> + intel_mmio_use_pci_bar(&mmio_data, pci_dev);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> printf("%s audio registers:\n\n", intel_get_device_info(devid)->codename);
> if (IS_VALLEYVIEW(devid)) {
> diff --git a/tools/intel_backlight.c b/tools/intel_backlight.c
> index bdbf9af3..1bd35f43 100644
> --- a/tools/intel_backlight.c
> +++ b/tools/intel_backlight.c
> @@ -35,12 +35,15 @@
> #include "intel_reg.h"
>
> /* XXX PCH only today */
> +static struct _mmio_data mmio_data;
> +void *igt_global_mmio;
>
> int main(int argc, char** argv)
> {
> uint32_t current, max;
>
> - intel_mmio_use_pci_bar(intel_get_pci_device());
> + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device());
> + igt_global_mmio = mmio_data.igt_mmio;
>
> current = INREG(igt_global_mmio, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
> max = INREG(igt_global_mmio, BLC_PWM_PCH_CTL2) >> 16;
> diff --git a/tools/intel_display_poller.c b/tools/intel_display_poller.c
> index e1094d39..af7e40cc 100644
> --- a/tools/intel_display_poller.c
> +++ b/tools/intel_display_poller.c
> @@ -59,6 +59,8 @@ enum test {
>
> static uint32_t vlv_offset;
> static uint16_t pipe_offset[3] = { 0, 0x1000, 0x2000, };
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> #define PIPE_REG(pipe, reg_a) (pipe_offset[(pipe)] + (reg_a))
>
> @@ -1187,7 +1189,8 @@ int main(int argc, char *argv[])
> break;
> }
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> printf("%s?\n", test_name(test, pipe, bit, test_pixelcount));
>
> @@ -1262,7 +1265,7 @@ int main(int argc, char *argv[])
> assert(0);
> }
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> if (quit)
> return 0;
> diff --git a/tools/intel_forcewaked.c b/tools/intel_forcewaked.c
> index 02fbf888..e52db5ed 100644
> --- a/tools/intel_forcewaked.c
> +++ b/tools/intel_forcewaked.c
> @@ -39,6 +39,8 @@
> #include "drmtest.h"
>
> bool daemonized;
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> #define INFO_PRINT(...) \
> do { \
> @@ -59,7 +61,7 @@ help(char *prog) {
> static int
> is_alive(void) {
> /* Read the timestamp, which should *almost* always be !0 */
> - return (intel_register_read(0x2358) != 0);
> + return (intel_register_read(&mmio_data, 0x2358) != 0);
> }
>
> int main(int argc, char *argv[])
> @@ -80,7 +82,8 @@ int main(int argc, char *argv[])
> INFO_PRINT("started daemon");
> }
>
> - ret = intel_register_access_init(intel_get_pci_device(), 1, -1);
> + ret = intel_register_access_init(&mmio_data, intel_get_pci_device(), 1, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
> if (ret) {
> INFO_PRINT("Couldn't init register access\n");
> exit(1);
> @@ -90,14 +93,15 @@ int main(int argc, char *argv[])
> while(1) {
> if (!is_alive()) {
> INFO_PRINT("gpu reset? restarting daemon\n");
> - intel_register_access_fini();
> - ret = intel_register_access_init(intel_get_pci_device(), 1, -1);
> + intel_register_access_fini(&mmio_data);
> + ret = intel_register_access_init(&mmio_data, intel_get_pci_device(), 1, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
> if (ret)
> INFO_PRINT("Reg access init fail\n");
> }
> sleep(1);
> }
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
> INFO_PRINT("Forcewake unlock\n");
>
> if (daemonized) {
> diff --git a/tools/intel_gpu_time.c b/tools/intel_gpu_time.c
> index 79240fd3..0cfc108b 100644
> --- a/tools/intel_gpu_time.c
> +++ b/tools/intel_gpu_time.c
> @@ -41,6 +41,8 @@
> #define SAMPLES_PER_SEC 10000
>
> static volatile int goddo;
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> static pid_t spawn(char **argv)
> {
> @@ -67,7 +69,8 @@ int main(int argc, char **argv)
> static struct rusage rusage;
> int status;
>
> - intel_mmio_use_pci_bar(intel_get_pci_device());
> + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device());
> + igt_global_mmio = mmio_data.igt_mmio;
>
> if (argc == 1) {
> fprintf(stderr, "usage: %s cmd [args...]\n", argv[0]);
> diff --git a/tools/intel_infoframes.c b/tools/intel_infoframes.c
> index 689f5faa..633a5e10 100644
> --- a/tools/intel_infoframes.c
> +++ b/tools/intel_infoframes.c
> @@ -262,6 +262,8 @@ const char *dip_frequency_names[] = {
> "reserved (invalid)"
> };
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
> struct pci_device *pci_dev;
> int gen = 0;
>
> @@ -1108,7 +1110,8 @@ int main(int argc, char *argv[])
> " perfectly: the Kernel might undo our changes.\n");
>
> pci_dev = intel_get_pci_device();
> - intel_register_access_init(pci_dev, 0, -1);
> + intel_register_access_init(&mmio_data, pci_dev, 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
> intel_check_pch();
>
> if (IS_GEN4(pci_dev->device_id))
> @@ -1256,6 +1259,6 @@ int main(int argc, char *argv[])
> }
>
> out:
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
> return ret;
> }
> diff --git a/tools/intel_l3_parity.c b/tools/intel_l3_parity.c
> index d8c997af..7a461a54 100644
> --- a/tools/intel_l3_parity.c
> +++ b/tools/intel_l3_parity.c
> @@ -44,6 +44,8 @@
> #include "intel_l3_parity.h"
>
> static unsigned int devid;
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
> /* L3 size is always a function of banks. The number of banks cannot be
> * determined by number of slices however */
> static inline int num_banks(void) {
> @@ -189,7 +191,8 @@ int main(int argc, char *argv[])
> if (intel_gen(devid) < 7 || IS_VALLEYVIEW(devid))
> exit(77);
>
> - assert(intel_register_access_init(intel_get_pci_device(), 0, device) == 0);
> + assert(intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, device) == 0);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> dir = igt_sysfs_open(device);
>
> @@ -211,7 +214,7 @@ int main(int argc, char *argv[])
> * now. Just be aware of this if for some reason a hang is reported
> * when using this tool.
> */
> - dft = intel_register_read(0xb038);
> + dft = intel_register_read(&mmio_data, 0xb038);
>
> while (1) {
> int c, option_index = 0;
> @@ -357,10 +360,11 @@ int main(int argc, char *argv[])
> assert(i < 2);
> dft |= i << 1; /* slice */
> dft |= 1 << 0; /* enable */
> - intel_register_write(0xb038, dft);
> + intel_register_write(&mmio_data, 0xb038, dft);
> break;
> case 'u':
> - intel_register_write(0xb038, dft & ~(1<<0));
> + intel_register_write(&mmio_data, 0xb038, dft &
> + ~(1 << 0));
> break;
> case 'L':
> break;
> @@ -369,7 +373,7 @@ int main(int argc, char *argv[])
> }
> }
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
> if (action == 'l')
> exit(EXIT_SUCCESS);
>
> diff --git a/tools/intel_lid.c b/tools/intel_lid.c
> index 2b597efb..b4f26b60 100644
> --- a/tools/intel_lid.c
> +++ b/tools/intel_lid.c
> @@ -52,6 +52,9 @@ enum lid_status {
> #define ACPI_BUTTON "/proc/acpi/button/"
> #define ACPI_LID "/proc/acpi/button/lid/"
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
> +
> static int i830_lvds_acpi_lid_state(void)
> {
> int fd;
> @@ -119,7 +122,8 @@ int main(int argc, char **argv)
> {
> int swf14, acpi_lid;
>
> - intel_mmio_use_pci_bar(intel_get_pci_device());
> + intel_mmio_use_pci_bar(&mmio_data, intel_get_pci_device());
> + igt_global_mmio = mmio_data.igt_mmio;
>
> while (1) {
> swf14 = INREG(igt_global_mmio, SWF14);
> diff --git a/tools/intel_panel_fitter.c b/tools/intel_panel_fitter.c
> index 26843d7c..9663d0cc 100644
> --- a/tools/intel_panel_fitter.c
> +++ b/tools/intel_panel_fitter.c
> @@ -35,6 +35,8 @@
> #include "intel_reg.h"
> #include "drmtest.h"
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
> int gen;
>
> uint32_t HTOTAL[] = { 0x60000, 0x61000, 0x62000 };
> @@ -280,7 +282,8 @@ int main (int argc, char *argv[])
> "solution that may or may not work. Use it at your own risk.\n");
>
> pci_dev = intel_get_pci_device();
> - intel_register_access_init(pci_dev, 0, -1);
> + intel_register_access_init(&mmio_data, pci_dev, 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
> devid = pci_dev->device_id;
>
> if (!HAS_PCH_SPLIT(devid)) {
> @@ -342,6 +345,6 @@ int main (int argc, char *argv[])
> }
>
> out:
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
> return ret;
> }
> diff --git a/tools/intel_perf_counters.c b/tools/intel_perf_counters.c
> index 50c4bce6..38f71419 100644
> --- a/tools/intel_perf_counters.c
> +++ b/tools/intel_perf_counters.c
> @@ -300,6 +300,8 @@ uint32_t *totals;
> uint32_t *last_counter;
> static drm_intel_bufmgr *bufmgr;
> struct intel_batchbuffer *batch;
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> /* DW0 */
> #define GEN5_MI_REPORT_PERF_COUNT ((0x26 << 23) | (3 - 2))
> @@ -483,12 +485,15 @@ main(int argc, char **argv)
>
> if (oacontrol) {
> /* Forcewake */
> - intel_register_access_init(intel_get_pci_device(), 0, fd);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(),
> + 0, fd);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> /* Enable performance counters */
> - intel_register_write(OACONTROL,
> - counter_format << OACONTROL_COUNTER_SELECT_SHIFT |
> - PERFORMANCE_COUNTER_ENABLE);
> + intel_register_write(&mmio_data, OACONTROL,
> + counter_format <<
> + OACONTROL_COUNTER_SELECT_SHIFT |
> + PERFORMANCE_COUNTER_ENABLE);
> }
>
> totals = calloc(counter_count, sizeof(uint32_t));
> @@ -520,10 +525,10 @@ main(int argc, char **argv)
>
> if (oacontrol) {
> /* Disable performance counters */
> - intel_register_write(OACONTROL, 0);
> + intel_register_write(&mmio_data, OACONTROL, 0);
>
> /* Forcewake */
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
> }
>
> free(totals);
> diff --git a/tools/intel_reg.c b/tools/intel_reg.c
> index 2e74b601..1c78af0b 100644
> --- a/tools/intel_reg.c
> +++ b/tools/intel_reg.c
> @@ -84,6 +84,9 @@ struct config {
> int verbosity;
> };
>
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
Sad trombone for these ugly ducklings. Same everywhere, really, but here
it hurts me because I put effort into avoiding *all* non-local data when
I wrote the tool.
There's struct config that gets passed around all over the place. That's
where this belongs. Don't take the shortcuts.
Or does igt_global_mmio have to be non-static? Then what's the point?
BR,
Jani.
> +
> /* port desc must have been set */
> static int set_reg_by_addr(struct config *config, struct reg *reg,
> uint32_t addr)
> @@ -390,7 +393,8 @@ static int read_register(struct config *config, struct reg *reg, uint32_t *valp)
> reg->port_desc.name);
> return -1;
> }
> - val = intel_iosf_sb_read(reg->port_desc.port, reg->addr);
> + val = intel_iosf_sb_read(&mmio_data, reg->port_desc.port,
> + reg->addr);
> break;
> default:
> fprintf(stderr, "port %d not supported\n", reg->port_desc.port);
> @@ -462,7 +466,8 @@ static int write_register(struct config *config, struct reg *reg, uint32_t val)
> reg->port_desc.name);
> return -1;
> }
> - intel_iosf_sb_write(reg->port_desc.port, reg->addr, val);
> + intel_iosf_sb_write(&mmio_data, reg->port_desc.port, reg->addr,
> + val);
> break;
> default:
> fprintf(stderr, "port %d not supported\n", reg->port_desc.port);
> @@ -556,9 +561,10 @@ static int intel_reg_read(struct config *config, int argc, char *argv[])
> }
>
> if (config->mmiofile)
> - intel_mmio_use_dump_file(config->mmiofile);
> + intel_mmio_use_dump_file(&mmio_data, config->mmiofile);
> else
> - intel_register_access_init(config->pci_dev, 0, -1);
> + intel_register_access_init(&mmio_data, config->pci_dev, 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> for (i = 1; i < argc; i++) {
> struct reg reg;
> @@ -574,7 +580,7 @@ static int intel_reg_read(struct config *config, int argc, char *argv[])
> }
> }
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> return EXIT_SUCCESS;
> }
> @@ -588,7 +594,8 @@ static int intel_reg_write(struct config *config, int argc, char *argv[])
> return EXIT_FAILURE;
> }
>
> - intel_register_access_init(config->pci_dev, 0, -1);
> + intel_register_access_init(&mmio_data, config->pci_dev, 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> for (i = 1; i < argc; i += 2) {
> struct reg reg;
> @@ -613,7 +620,7 @@ static int intel_reg_write(struct config *config, int argc, char *argv[])
> write_register(config, ®, val);
> }
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> return EXIT_SUCCESS;
> }
> @@ -624,9 +631,10 @@ static int intel_reg_dump(struct config *config, int argc, char *argv[])
> int i;
>
> if (config->mmiofile)
> - intel_mmio_use_dump_file(config->mmiofile);
> + intel_mmio_use_dump_file(&mmio_data, config->mmiofile);
> else
> - intel_register_access_init(config->pci_dev, 0, -1);
> + intel_register_access_init(&mmio_data, config->pci_dev, 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> for (i = 0; i < config->regcount; i++) {
> reg = &config->regs[i];
> @@ -638,7 +646,7 @@ static int intel_reg_dump(struct config *config, int argc, char *argv[])
> dump_register(config, &config->regs[i]);
> }
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> return EXIT_SUCCESS;
> }
> @@ -652,7 +660,8 @@ static int intel_reg_snapshot(struct config *config, int argc, char *argv[])
> return EXIT_FAILURE;
> }
>
> - intel_mmio_use_pci_bar(config->pci_dev);
> + intel_mmio_use_pci_bar(&mmio_data, config->pci_dev);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> /* XXX: error handling */
> if (write(1, igt_global_mmio, config->pci_dev->regions[mmio_bar].size) == -1)
> diff --git a/tools/intel_reg_checker.c b/tools/intel_reg_checker.c
> index b14a06ea..c8831901 100644
> --- a/tools/intel_reg_checker.c
> +++ b/tools/intel_reg_checker.c
> @@ -32,6 +32,9 @@
> static uint32_t devid;
> static int gen;
>
> +static struct _mmio_data mmio_data;
> +void *igt_global_mmio;
> +
> static uint32_t
> read_and_print_reg(const char *name, uint32_t reg)
> {
> @@ -345,7 +348,8 @@ int main(int argc, char** argv)
>
> dev = intel_get_pci_device();
> devid = dev->device_id;
> - intel_mmio_use_pci_bar(dev);
> + intel_mmio_use_pci_bar(&mmio_data, dev);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> if (IS_GEN7(devid))
> gen = 7;
> diff --git a/tools/intel_watermark.c b/tools/intel_watermark.c
> index 00bdd120..3f267fa6 100644
> --- a/tools/intel_watermark.c
> +++ b/tools/intel_watermark.c
> @@ -35,6 +35,8 @@
>
> static uint32_t display_base;
> static uint32_t devid;
> +void *igt_global_mmio;
> +static struct _mmio_data mmio_data;
>
> static uint32_t read_reg(uint32_t addr)
> {
> @@ -249,7 +251,8 @@ static void skl_wm_dump(void)
> uint32_t plane_ctl[num_pipes][max_planes];
> uint32_t wm_linetime[num_pipes];
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> for (pipe = 0; pipe < num_pipes; pipe++) {
> int num_planes = skl_num_planes(devid, pipe);
> @@ -469,7 +472,8 @@ static void ilk_wm_dump(void)
> int num_pipes = intel_gen(devid) >= 7 ? 3 : 2;
> struct ilk_wm wm = {};
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> for (i = 0; i < num_pipes; i++) {
> dspcntr[i] = read_reg(0x70180 + i * 0x1000);
> @@ -505,7 +509,7 @@ static void ilk_wm_dump(void)
> if (IS_BROADWELL(devid) || IS_HASWELL(devid))
> wm_misc = read_reg(0x45260);
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> for (i = 0; i < num_pipes; i++)
> printf(" WM_PIPE_%c = 0x%08x\n", pipe_name(i), wm_pipe[i]);
> @@ -619,7 +623,8 @@ static void vlv_wm_dump(void)
> uint32_t dsp_ss_pm, ddr_setup2;
> struct gmch_wm wms[MAX_PLANE] = {};
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> dsparb = read_reg(0x70030);
> dsparb2 = read_reg(0x70060);
> @@ -650,13 +655,13 @@ static void vlv_wm_dump(void)
>
> ddl3 = read_reg(0x70058);
>
> - intel_punit_read(0x36, &dsp_ss_pm);
> - intel_punit_read(0x139, &ddr_setup2);
> + intel_punit_read(&mmio_data, 0x36, &dsp_ss_pm);
> + intel_punit_read(&mmio_data, 0x139, &ddr_setup2);
> } else {
> fw7 = read_reg(0x7007c);
> }
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> printf(" FW1 = 0x%08x\n", fw1);
> printf(" FW2 = 0x%08x\n", fw2);
> @@ -835,7 +840,8 @@ static void g4x_wm_dump(void)
> uint32_t mi_arb_state;
> struct gmch_wm wms[MAX_PLANE] = {};
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> dspacntr = read_reg(0x70180);
> dspbcntr = read_reg(0x71180);
> @@ -846,7 +852,7 @@ static void g4x_wm_dump(void)
> mi_display_power_down = read_reg(0x20e0);
> mi_arb_state = read_reg(0x20e4);
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> printf(" DSPACNTR = 0x%08x\n", dspacntr);
> printf(" DSPBCNTR = 0x%08x\n", dspbcntr);
> @@ -921,7 +927,8 @@ static void gen4_wm_dump(void)
> uint32_t mi_arb_state;
> struct gmch_wm wms[MAX_PLANE] = {};
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> dsparb = read_reg(0x70030);
> fw1 = read_reg(0x70034);
> @@ -930,7 +937,7 @@ static void gen4_wm_dump(void)
> mi_display_power_down = read_reg(0x20e0);
> mi_arb_state = read_reg(0x20e4);
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> printf(" FW1 = 0x%08x\n", fw1);
> printf(" FW2 = 0x%08x\n", fw2);
> @@ -992,7 +999,8 @@ static void pnv_wm_dump(void)
> uint32_t cbr;
> struct gmch_wm wms[MAX_PLANE] = {};
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> dsparb = read_reg(0x70030);
> fw1 = read_reg(0x70034);
> @@ -1002,7 +1010,7 @@ static void pnv_wm_dump(void)
> mi_display_power_down = read_reg(0x20e0);
> mi_arb_state = read_reg(0x20e4);
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> printf(" DSPARB = 0x%08x\n", dsparb);
> printf(" FW1 = 0x%08x\n", fw1);
> @@ -1082,7 +1090,8 @@ static void gen3_wm_dump(void)
> uint32_t mi_arb_state;
> struct gmch_wm wms[MAX_PLANE] = {};
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> dsparb = read_reg(0x70030);
> instpm = read_reg(0x20c0);
> @@ -1090,7 +1099,7 @@ static void gen3_wm_dump(void)
> fw_blc_self = read_reg(0x20e0);
> mi_arb_state = read_reg(0x20e4);
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> printf(" DSPARB = 0x%08x\n", dsparb);
> printf(" FW_BLC = 0x%016" PRIx64 "\n", fw_blc);
> @@ -1151,7 +1160,8 @@ static void gen2_wm_dump(void)
> uint32_t mi_state;
> struct gmch_wm wms[MAX_PLANE] = {};
>
> - intel_register_access_init(intel_get_pci_device(), 0, -1);
> + intel_register_access_init(&mmio_data, intel_get_pci_device(), 0, -1);
> + igt_global_mmio = mmio_data.igt_mmio;
>
> dsparb = read_reg(0x70030);
> mem_mode = read_reg(0x20cc);
> @@ -1159,7 +1169,7 @@ static void gen2_wm_dump(void)
> fw_blc_self = read_reg(0x20e0);
> mi_state = read_reg(0x20e4);
>
> - intel_register_access_fini();
> + intel_register_access_fini(&mmio_data);
>
> printf(" DSPARB = 0x%08x\n", dsparb);
> printf(" MEM_MODE = 0x%08x\n", mem_mode);
--
Jani Nikula, Intel Open Source Graphics Center
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