[igt-dev] [RFC PATCH 1/1] i915/gem_tiled_blits: Avoid SET_TILING on Gen 9+

[Vanshidhar Konda]

The test currently uses SET_TILING IOCTL for buffer objects. This IOCTL
is not supported on Gen12 and beyond. Update the test to use
igt_blitter_fast_copy__raw() on Gen 9+ - this avoids have to use
SET_TILING IOCTL as well as increases the usage of
igt_blitter_fast_copy__raw() method available in the library.

Signed-off-by: Vanshidhar Konda <vanshidhar.r.konda at intel.com>
---
 tests/i915/gem_tiled_blits.c | 44 ++++++++++++++++++++++++++++--------
 1 file changed, 35 insertions(+), 9 deletions(-)

diff --git a/tests/i915/gem_tiled_blits.c b/tests/i915/gem_tiled_blits.c
index df0699f3..f761c818 100644
--- a/tests/i915/gem_tiled_blits.c
+++ b/tests/i915/gem_tiled_blits.c
@@ -60,6 +60,26 @@ IGT_TEST_DESCRIPTION("Test doing many tiled blits, with a working set larger"
 static drm_intel_bufmgr *bufmgr;
 struct intel_batchbuffer *batch;
 static int width = 512, height = 512;
+int fd;
+int device_gen;
+
+static void copy_bo(struct intel_batchbuffer *b,
+		    drm_intel_bo *dst, uint32_t dst_tiling,
+		    drm_intel_bo *src, uint32_t src_tiling,
+		    int size)
+{
+	if (device_gen < 9) {
+		intel_copy_bo(b, dst, src, size);
+	}
+	else {
+		igt_blitter_fast_copy__raw(fd,
+					   src->handle, 0, 4096,
+					   src_tiling, 0, 0, 1024,
+					   (width*height*4)/4096, 32,
+					   dst->handle, 0, 4096,
+					   dst_tiling, 0, 0);
+	}
+}
 
 static drm_intel_bo *
 create_bo(uint32_t start_val)
@@ -70,8 +90,10 @@ create_bo(uint32_t start_val)
 	int i;
 
 	bo = drm_intel_bo_alloc(bufmgr, "tiled bo", 1024 * 1024, 4096);
-	do_or_die(drm_intel_bo_set_tiling(bo, &tiling, width * 4));
-	igt_assert(tiling == I915_TILING_X);
+	if (device_gen < 9) {
+		do_or_die(drm_intel_bo_set_tiling(bo, &tiling, width * 4));
+		igt_assert(tiling == I915_TILING_X);
+	}
 
 	linear_bo = drm_intel_bo_alloc(bufmgr, "linear src", 1024 * 1024, 4096);
 
@@ -82,7 +104,8 @@ create_bo(uint32_t start_val)
 		linear[i] = start_val++;
 	drm_intel_bo_unmap(linear_bo);
 
-	intel_copy_bo (batch, bo, linear_bo, width*height*4);
+	copy_bo(batch, bo, I915_TILING_X,
+		linear_bo, I915_TILING_NONE, width*height*4);
 
 	drm_intel_bo_unreference(linear_bo);
 
@@ -99,7 +122,8 @@ check_bo(drm_intel_bo *bo, uint32_t val)
 
 	linear_bo = drm_intel_bo_alloc(bufmgr, "linear dst", 1024 * 1024, 4096);
 
-	intel_copy_bo(batch, linear_bo, bo, width*height*4);
+	copy_bo(batch, linear_bo, I915_TILING_NONE,
+		bo, I915_TILING_X, width*height*4);
 
 	do_or_die(drm_intel_bo_map(linear_bo, 0));
 	linear = linear_bo->virtual;
@@ -146,7 +170,8 @@ static void run_test(int count)
 		if (src == dst)
 			continue;
 
-		intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
+		copy_bo(batch, bo[dst], I915_TILING_X,
+			bo[src], I915_TILING_X, width*height*4);
 		bo_start_val[dst] = bo_start_val[src];
 	}
 	for (i = 0; i < count; i++)
@@ -168,7 +193,8 @@ static void run_test(int count)
 		if (src == dst)
 			continue;
 
-		intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
+		copy_bo(batch, bo[dst], I915_TILING_X,
+			bo[src], I915_TILING_X, width*height*4);
 		bo_start_val[dst] = bo_start_val[src];
 	}
 	for (i = 0; i < count; i++)
@@ -182,7 +208,8 @@ static void run_test(int count)
 		if (src == dst)
 			continue;
 
-		intel_copy_bo(batch, bo[dst], bo[src], width*height*4);
+		copy_bo(batch, bo[dst], I915_TILING_X,
+			bo[src], I915_TILING_X, width*height*4);
 		bo_start_val[dst] = bo_start_val[src];
 	}
 	for (i = 0; i < count; i++) {
@@ -196,8 +223,6 @@ static void run_test(int count)
 
 #define MAX_32b ((1ull << 32) - 4096)
 
-int fd;
-
 igt_main
 {
 	igt_fixture {
@@ -209,6 +234,7 @@ igt_main
 		drm_intel_bufmgr_gem_enable_reuse(bufmgr);
 		drm_intel_bufmgr_gem_set_vma_cache_size(bufmgr, 32);
 		batch = intel_batchbuffer_alloc(bufmgr, intel_get_drm_devid(fd));
+		device_gen = intel_gen(intel_get_drm_devid(fd));
 	}
 
 	igt_subtest("basic")
-- 
2.24.0