[igt-dev] [PATCH i-g-t] tests/i915_pm_dc: Increase timeout and poll interval

[Imre Deak]

On Wed, Nov 13, 2019 at 04:05:18PM +0530, Anshuamn Gupta wrote:
> On 2019-10-23 at 22:10:02 +0300, Imre Deak wrote:
> > The eDP panel power cycle delay prevents DC entry after a full modeset,
> > which makes the test fail on some panels. Let's increase the timeout to
> > take into account that delay (atm in the worst case the power cycle
> > delay is 3 seconds) and also increase the polling interval to give more
> > time for the device to enter a low power state.
>
> IMHO how about exposing the panel_power_cycle_delay delay too in
> i915_panel_timings attribute which can used by the igt to wait for
> time which is required.  It can save some time for IGT ?
> i915_panel_timings has already exposing the other panel timings for
> debug purpose.

Ok, although waiting for the timeout actually is the exception, but it
makes sense to expose the power cycle delay with the rest of timings
anyway. We can also make the wait condition stricter then; let's use a
timeout that is 2x the power cycle delay in that case too though.

> > 
> > Cc: Anshuman Gupta <anshuman.gupta at intel.com>
> > Signed-off-by: Imre Deak <imre.deak at intel.com>
> > ---
> >  tests/i915/i915_pm_dc.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> > index ce3319b7..ef96a86e 100644
> > --- a/tests/i915/i915_pm_dc.c
> > +++ b/tests/i915/i915_pm_dc.c
> > @@ -153,7 +153,7 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
> >  static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
> >  {
> >  	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> > -			prev_dc_count, 3000, 100);
> > +			prev_dc_count, 6000, 1000);
> >  }
> >  
> >  static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
> > -- 
> > 2.17.1
> >