[igt-dev] [PATCH i-g-t 2/3] Add a new IGT test to validate DC3CO state

Anshuman Gupta anshuman.gupta at intel.com
Thu Oct 3 11:25:34 UTC 2019


On 2019-10-03 at 13:15:08 +0530, Jeevan B wrote:
> Add a subtest for DC3CO video playback case
> to generate selective frame update and validate
> that system stays in DC3CO state during execution.
> 
> v2: Changed PSR2 idle check to sleep check and addressed
> cosmetic changes.
> 
> v3: Renamed a function and restructured code according
> to Anshuman’s comments.
> 
> v4: Cosmetic changes.
> 
> Signed-off-by: Jeevan B <jeevan.b at intel.com>
> ---
>  lib/igt_psr.c           |  11 ++++
>  lib/igt_psr.h           |   1 +
>  tests/i915/i915_pm_dc.c | 149 +++++++++++++++++++++++++++++++++++++++++++++++-
>  3 files changed, 160 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/igt_psr.c b/lib/igt_psr.c
> index b92ea73..7806ce9 100644
> --- a/lib/igt_psr.c
> +++ b/lib/igt_psr.c
> @@ -36,6 +36,17 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
>  	return strstr(buf, state);
>  }
>  
> +bool psr2_active_sleep_check(int debugfs_fd)
> +{
> +	char buf[PSR_STATUS_MAX_LEN];
> +	const char *state = "SLEEP";
> +
> +	igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
> +				sizeof(buf));
> +
> +	return strstr(buf, state);
> +}
> +
>  static inline const char *psr_active_state_get(enum psr_mode mode)
>  {
>  	return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";
> diff --git a/lib/igt_psr.h b/lib/igt_psr.h
> index ca38573..a0627dc 100644
> --- a/lib/igt_psr.h
> +++ b/lib/igt_psr.h
> @@ -35,6 +35,7 @@ enum psr_mode {
>  	PSR_MODE_2
>  };
>  
> +bool psr2_active_sleep_check(int debugfs_fd);
>  bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
>  bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
>  bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);
> diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
> index 19d8a78..c02c02e 100644
> --- a/tests/i915/i915_pm_dc.c
> +++ b/tests/i915/i915_pm_dc.c
> @@ -38,13 +38,20 @@
>  #define CHECK_DC6	2
>  #define CHECK_DC3CO     4
>  
> +/*Number of Frames Video Playback*/
> +#define VIDEO_FRAMES 100
> +
> +typedef struct {
> +	double r, g, b;
> +} color_t;
> +
>  typedef struct {
>  	int drm_fd;
>  	int msr_fd;
>  	int debugfs_fd;
>  	uint32_t devid;
>  	igt_display_t display;
> -	struct igt_fb fb_white;
> +	struct igt_fb fb_white, fb_rgb, fb_rgr;
>  	enum psr_mode op_psr_mode;
>  	drmModeModeInfo *mode;
>  	igt_output_t *output;
> @@ -114,6 +121,43 @@ static void cleanup_dc_psr(data_t *data)
>  	igt_remove_fb(data->drm_fd, &data->fb_white);
>  }
>  
> +static void cleanup_dc3co(data_t *data)
> +{
> +	igt_plane_t *primary;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +					    DRM_PLANE_TYPE_PRIMARY);
> +	igt_plane_set_fb(primary, NULL);
> +
> +	/* Clear Frame Buffers */
> +	igt_display_commit(&data->display);
> +	igt_remove_fb(data->drm_fd, &data->fb_rgb);
> +	igt_remove_fb(data->drm_fd, &data->fb_rgr);
> +}
> +
> +static void paint_rectangles(data_t *data,
> +			     drmModeModeInfo *mode,
> +			     color_t *colors,
> +			     igt_fb_t *fb)
> +{
> +	cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
> +	int i, l = mode->hdisplay / 3;
> +	int rows_remaining = mode->hdisplay % 3;
> +
> +	/* Paint 3 solid rectangles. */
> +	for (i = 0 ; i < 3; i++) {
> +		igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
> +				colors[i].r, colors[i].g, colors[i].b);
> +	}
> +
> +	if (rows_remaining > 0)
> +		igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
> +				colors[i - 1].r, colors[i - 1].g,
> +				colors[i - 1].b);
> +
> +	igt_put_cairo_ctx(data->drm_fd, fb, cr);
> +}
> +
>  static void setup_primary(data_t *data)
>  {
>  	igt_plane_t *primary;
> @@ -131,6 +175,25 @@ static void setup_primary(data_t *data)
>  	igt_display_commit(&data->display);
>  }
>  
> +static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
> +{
> +	igt_plane_t *primary;
> +	int fb_id;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +					    DRM_PLANE_TYPE_PRIMARY);
> +
> +	igt_plane_set_fb(primary, NULL);
	Do we need to pair primary plane with NULL framebuffer here?
	We are not doing any commit here, i am not sure about it.
	@ankit can u please comment here.
> +	fb_id = igt_create_fb(data->drm_fd,
> +			      data->mode->hdisplay,
> +			      data->mode->vdisplay,
> +			      DRM_FORMAT_XRGB8888,
> +			      LOCAL_DRM_FORMAT_MOD_NONE,
> +			      fb);
> +	igt_assert(fb_id);
> +	paint_rectangles(data, data->mode, fb_color, fb);
> +}
> +
>  static uint32_t get_dc_counter(char *dc_data)
>  {
>  	char *e;
> @@ -171,6 +234,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
>  	return get_dc_counter(str);
>  }
>  
> +static bool psr2_wait_sleep_entry(int debugfs_fd)
> +{
> +	return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
> +}
> +
>  static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
>  {
>  	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
> @@ -187,6 +255,78 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
>  		     "%s state is not achieved\n", tmp);
>  }
>  
> +static void setup_vpb(data_t *data)
> +{
> +	color_t red_green_blue[] = {
> +		{ 1.0, 0.0, 0.0 },
> +		{ 0.0, 1.0, 0.0 },
> +		{ 0.0, 0.0, 1.0 },
> +	};
> +	color_t red_green_red[] = {
> +		{ 1.0, 0.0, 0.0 },
> +		{ 0.0, 1.0, 0.0 },
> +		{ 1.0, 0.0, 0.0 },
> +	};
> +
> +	setup_output(data);
	please move this to after setup_dc3co() in test_dc3co_vpb_simulation()
> +
	we do not need space here.
> +	create_color_fb(data, &data->fb_rgb, red_green_blue);
> +	create_color_fb(data, &data->fb_rgr, red_green_red);
> +}
> +
> +static void run_videoplayback(data_t *data, int dc_flag)
> +{
> +	igt_plane_t *primary;
> +	uint32_t dc3co_prev_cnt;
> +	int i, delay;
> +
> +	primary = igt_output_get_plane_type(data->output,
> +					    DRM_PLANE_TYPE_PRIMARY);
> +
> +	igt_plane_set_fb(primary, NULL);
> +
	we do not need space here too.
> +	dc3co_prev_cnt = read_dc_counter(data->drm_fd, dc_flag);
> +	/* Calculate delay to generate idle frame */
	Please mention the delay is for an idle frame in usec in comment.
> +	delay = ((1000 * 1000) / data->mode->vrefresh);
> +
> +	for (i = 0; i < VIDEO_FRAMES; i++) {
> +		if (i % 2 == 0) {
> +			igt_plane_set_fb(primary, &data->fb_rgb);
> +			igt_display_commit(&data->display);
> +		} else {
> +			igt_plane_set_fb(primary, &data->fb_rgr);
> +			igt_display_commit(&data->display);
> +		}
> +
> +		usleep(delay);
> +		igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
> +	}
	A space require here after each block of code.
> +	check_dc_counter(data->drm_fd, dc_flag, dc3co_prev_cnt);
> +}
> +
> +static void setup_dc3co(data_t *data)
> +{
> +	igt_require(IS_TIGERLAKE(data->devid));
> +	data->op_psr_mode = PSR_MODE_2;
> +	psr_enable(data->debugfs_fd, data->op_psr_mode);
> +	igt_require_f(edp_psr2_enabled(data),
> +		      "PSR2 is not enabled\n");
> +}
> +
> +static void test_dc3co_vpb_simulation(data_t *data, int dc_flag)
> +{
> +	uint32_t dc5_cnt_before, dc5_cnt_after;
> +
> +	setup_dc3co(data);
> +	setup_vpb(data);
> +	dc5_cnt_before = read_dc_counter(data->drm_fd, CHECK_DC5);
> +	run_videoplayback(data, dc_flag);
> +	dc5_cnt_after = read_dc_counter(data->drm_fd, CHECK_DC5);
> +	igt_assert_f(dc5_cnt_after == dc5_cnt_before,
> +			"DC State moved to DC5\n");
	Align this to open parenthesis.
> +	cleanup_dc3co(data);
> +}
> +
>  static void test_dc_state_psr(data_t *data, int dc_flag)
>  {
>  	uint32_t dc_counter_before_psr;
> @@ -288,6 +428,13 @@ int main(int argc, char *argv[])
>  			     "Can't open /dev/cpu/0/msr.\n");
>  	}
>  
> +	igt_describe("This test simulate videoplay back "
			Typo video playback.
> +		     "in order to validate DC3CO state "
> +		     "while PSR2 is active and in SLEEP state");
> +	igt_subtest("dc3co-vpb-simulation") {
> +		test_dc3co_vpb_simulation(&data, CHECK_DC3CO);
> +	}
> +
>  	igt_describe("This test validates display engine entry to DC5 state "
>  		     "while PSR is active");
>  	igt_subtest("dc5-psr") {
With above feedback and comment patch is looks good to me.
Reviewed-by: Anshuman Gupta <anshuman.gupta at intel.com>
> -- 
> 2.7.4
> 


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