[igt-dev] [PATCH i-g-t] tests/i915_pm_dc: Increase timeout and poll interval

[Imre Deak]

The eDP panel power cycle delay prevents DC entry after a full modeset,
which makes the test fail on some panels. Let's increase the timeout to
take into account that delay (atm in the worst case the power cycle
delay is 3 seconds) and also increase the polling interval to give more
time for the device to enter a low power state.

Cc: Anshuman Gupta <anshuman.gupta at intel.com>
Signed-off-by: Imre Deak <imre.deak at intel.com>
---
 tests/i915/i915_pm_dc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/i915/i915_pm_dc.c b/tests/i915/i915_pm_dc.c
index ce3319b7..ef96a86e 100644
--- a/tests/i915/i915_pm_dc.c
+++ b/tests/i915/i915_pm_dc.c
@@ -153,7 +153,7 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 {
 	return igt_wait(read_dc_counter(drm_fd, dc_flag) >
-			prev_dc_count, 3000, 100);
+			prev_dc_count, 6000, 1000);
 }
 
 static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
-- 
2.17.1