[igt-dev] [PATCH] [PATCH i-g-t]test/i915/gem_pipe_control_store_loop: Removal of test
ranjeet kumar
ranjeet1.kumar at intel.com
Thu Feb 6 11:01:10 UTC 2020
This test doesnt have any dependecy with other tests, hence is called out as redundant.
This test has already been covered by gem_sync, hence it is being removed.
gem_pipe_control_store_loop is not covered by gen2/gen3.
Cc: Argenziano Antonio <antonio.argenziano at intel.com>
Cc: Tahvanainen Jari <jari.tahvanainen at intel.com>
Signed-off-by: Kumar Ranjeet1 <ranjeet1.kumar at intel.com>
---
tests/Makefile.sources | 3 -
tests/i915/gem_pipe_control_store_loop.c | 196 -----------------------
tests/meson.build | 1 -
3 files changed, 200 deletions(-)
delete mode 100644 tests/i915/gem_pipe_control_store_loop.c
diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 9d86f853..99b1281c 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -318,9 +318,6 @@ gem_mmap_wc_SOURCES = i915/gem_mmap_wc.c
TESTS_progs += gem_partial_pwrite_pread
gem_partial_pwrite_pread_SOURCES = i915/gem_partial_pwrite_pread.c
-TESTS_progs += gem_pipe_control_store_loop
-gem_pipe_control_store_loop_SOURCES = i915/gem_pipe_control_store_loop.c
-
TESTS_progs += gem_ppgtt
gem_ppgtt_SOURCES = i915/gem_ppgtt.c
diff --git a/tests/i915/gem_pipe_control_store_loop.c b/tests/i915/gem_pipe_control_store_loop.c
deleted file mode 100644
index e44e9fb5..00000000
--- a/tests/i915/gem_pipe_control_store_loop.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright © 2011 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Daniel Vetter <daniel.vetter at ffwll.ch> (based on gem_storedw_*.c)
- *
- */
-
-/*
- * Testcase: (TLB-)Coherency of pipe_control QW writes
- *
- * Writes a counter-value into an always newly allocated target bo (by disabling
- * buffer reuse). Decently trashes on tlb inconsistencies, too.
- */
-#include "igt.h"
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <fcntl.h>
-#include <inttypes.h>
-#include <errno.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include "drm.h"
-#include "intel_bufmgr.h"
-
-IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes.");
-
-static drm_intel_bufmgr *bufmgr;
-struct intel_batchbuffer *batch;
-uint32_t devid;
-
-#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
-#define PIPE_CONTROL_WRITE_IMMEDIATE (1<<14)
-#define PIPE_CONTROL_WRITE_TIMESTAMP (3<<14)
-#define PIPE_CONTROL_DEPTH_STALL (1<<13)
-#define PIPE_CONTROL_WC_FLUSH (1<<12)
-#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
-#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
-#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
-#define PIPE_CONTROL_CS_STALL (1<<20)
-#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
-
-/* Like the store dword test, but we create new command buffers each time */
-static void
-store_pipe_control_loop(bool preuse_buffer, int timeout)
-{
- int val = 0;
- uint32_t *buf;
- drm_intel_bo *target_bo;
-
- igt_until_timeout(timeout) {
- /* we want to check tlb consistency of the pipe_control target,
- * so get a new buffer every time around */
- target_bo = drm_intel_bo_alloc(bufmgr, "target bo", 4096, 4096);
- igt_assert(target_bo);
-
- if (preuse_buffer) {
- COLOR_BLIT_COPY_BATCH_START(0);
- OUT_BATCH((3 << 24) | (0xf0 << 16) | 64);
- OUT_BATCH(0);
- OUT_BATCH(1 << 16 | 1);
-
- /*
- * IMPORTANT: We need to preuse the buffer in a
- * different domain than what the pipe control write
- * (and kernel wa) uses!
- */
- OUT_RELOC_FENCED(target_bo,
- I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
- 0);
- OUT_BATCH(0xdeadbeef);
- ADVANCE_BATCH();
-
- intel_batchbuffer_flush(batch);
- }
-
- /* gem_storedw_batches_loop.c is a bit overenthusiastic with
- * creating new batchbuffers - with buffer reuse disabled, the
- * support code will do that for us. */
- if (batch->gen >= 8) {
- BEGIN_BATCH(4, 1);
- OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
- OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
- OUT_RELOC_FENCED(target_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- PIPE_CONTROL_GLOBAL_GTT);
- OUT_BATCH(val); /* write data */
- ADVANCE_BATCH();
-
- } else if (batch->gen >= 6) {
- /* work-around hw issue, see intel_emit_post_sync_nonzero_flush
- * in mesa sources. */
- BEGIN_BATCH(4, 1);
- OUT_BATCH(GFX_OP_PIPE_CONTROL);
- OUT_BATCH(PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_STALL_AT_SCOREBOARD);
- OUT_BATCH(0); /* address */
- OUT_BATCH(0); /* write data */
- ADVANCE_BATCH();
-
- BEGIN_BATCH(4, 1);
- OUT_BATCH(GFX_OP_PIPE_CONTROL);
- OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
- OUT_RELOC(target_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- PIPE_CONTROL_GLOBAL_GTT);
- OUT_BATCH(val); /* write data */
- ADVANCE_BATCH();
- } else if (batch->gen >= 4) {
- BEGIN_BATCH(4, 1);
- OUT_BATCH(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_WC_FLUSH |
- PIPE_CONTROL_TC_FLUSH |
- PIPE_CONTROL_WRITE_IMMEDIATE | 2);
- OUT_RELOC(target_bo,
- I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
- PIPE_CONTROL_GLOBAL_GTT);
- OUT_BATCH(val);
- OUT_BATCH(0xdeadbeef);
- ADVANCE_BATCH();
- }
-
- intel_batchbuffer_flush_on_ring(batch, 0);
-
- drm_intel_bo_map(target_bo, 1);
-
- buf = target_bo->virtual;
- igt_assert(buf[0] == val);
-
- drm_intel_bo_unmap(target_bo);
- /* Make doublesure that this buffer won't get reused. */
- drm_intel_bo_disable_reuse(target_bo);
- drm_intel_bo_unreference(target_bo);
-
- val++;
- }
-}
-
-int fd;
-
-igt_main
-{
- igt_fixture {
- fd = drm_open_driver(DRIVER_INTEL);
- igt_require_gem(fd);
- gem_require_blitter(fd);
-
- devid = intel_get_drm_devid(fd);
-
- bufmgr = drm_intel_bufmgr_gem_init(fd, 4096);
- igt_assert(bufmgr);
-
- igt_skip_on(IS_GEN2(devid) || IS_GEN3(devid));
- igt_skip_on(devid == PCI_CHIP_I965_G); /* has totally broken pipe control */
-
- /* IMPORTANT: No call to
- * drm_intel_bufmgr_gem_enable_reuse(bufmgr);
- * here because we wan't to have fresh buffers (to trash the tlb)
- * every time! */
-
- batch = intel_batchbuffer_alloc(bufmgr, devid);
- igt_assert(batch);
- }
-
- igt_subtest("fresh-buffer")
- store_pipe_control_loop(false, 2);
-
- igt_subtest("reused-buffer")
- store_pipe_control_loop(true, 2);
-
- igt_fixture {
- intel_batchbuffer_free(batch);
- drm_intel_bufmgr_destroy(bufmgr);
-
- close(fd);
- }
-}
diff --git a/tests/meson.build b/tests/meson.build
index dc16665b..1102d0a3 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -171,7 +171,6 @@ i915_progs = [
'gem_mmap_gtt',
'gem_mmap_wc',
'gem_partial_pwrite_pread',
- 'gem_pipe_control_store_loop',
'gem_ppgtt',
'gem_pread',
'gem_pread_after_blit',
--
2.25.0
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