[igt-dev] [PATCH i-g-t v9 14/17] lib/intel_batchbuffer: change alignment constraints on gen4

[Zbigniew Kempczyński]

Gen4 requires bigger alignment on tiled buffers. Change to 0x8000
(similar relocation code does for gen3).

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
---
 lib/intel_batchbuffer.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 3ae369b7..89fd754c 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1578,6 +1578,12 @@ intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write)
 		obj->alignment = 0x10000;
 	}
 
+	/* For gen3 ensure tiled buffers are aligned to 0x8000 */
+	if (ibb->gen == 3 && buf->tiling) {
+		obj->offset &= ~(0x8000 - 1);
+		obj->alignment = 0x8000;
+	}
+
 	/* Update address in intel_buf buffer */
 	buf->addr.offset = obj->offset;
 
-- 
2.26.0