[igt-dev] [PATCH i-g-t v10 14/17] lib/intel_batchbuffer: change alignment constraints on gen3

[Zbigniew Kempczyński]

Gen3 requires bigger alignment on tiled buffers. Change to power
of two sized (starting from 1MB).

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
---
 lib/intel_batchbuffer.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index 3ae369b7..cd5278b0 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1578,6 +1578,16 @@ intel_bb_add_intel_buf(struct intel_bb *ibb, struct intel_buf *buf, bool write)
 		obj->alignment = 0x10000;
 	}
 
+	/* For gen3 ensure tiled buffers are aligned to power of two size */
+	if (ibb->gen == 3 && buf->tiling) {
+		uint64_t alignment = 1024 * 1024;
+
+		while (alignment < buf->surface[0].size)
+			alignment <<= 1;
+		obj->offset &= ~(alignment - 1);
+		obj->alignment = alignment;
+	}
+
 	/* Update address in intel_buf buffer */
 	buf->addr.offset = obj->offset;
 
-- 
2.26.0