[igt-dev] [PATCH 1/2] lib: Add stride and size calculation for amdgpu + tiling

[Kazlauskas, Nicholas]

On 2020-12-16 6:02 p.m., Sung Joon Kim wrote:
> For amdgpu, we need to calculate the stride and size of framebuffer correctly during non-linear tiling mode
> 
> Signed-off-by: Sung Joon Kim <sungkim at amd.com>
> ---
>   lib/igt_fb.c | 11 +++++++++++
>   1 file changed, 11 insertions(+)
> 
> diff --git a/lib/igt_fb.c b/lib/igt_fb.c
> index 422a9e06..b99e8d07 100644
> --- a/lib/igt_fb.c
> +++ b/lib/igt_fb.c
> @@ -670,6 +670,11 @@ static uint32_t calc_plane_stride(struct igt_fb *fb, int plane)
>   		 * so the easiest way is to align the luma stride to 256.
>   		 */
>   		return ALIGN(min_stride, 256);
> +	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return ALIGN(min_stride, 512);
>   	} else if (is_gen12_ccs_cc_plane(fb, plane)) {
>   		/* clear color always fixed to 64 bytes */
>   		return 64;
> @@ -710,6 +715,12 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
>   		size = roundup_power_of_two(size);
>   
>   		return size;
> +	} else if (fb->modifier != LOCAL_DRM_FORMAT_MOD_NONE && is_amdgpu_device(fb->fd)) {
> +		/*
> +		 * For amdgpu device with tiling mode
> +		 */
> +		return (uint64_t) fb->strides[plane] *
> +			ALIGN(fb->plane_height[plane], 512);

Is the requirement that only the stride be aligned to 512? Are you sure 
we need to bypass the regular plane size calculation here?

Regards,
Nicholas Kazlauskas

>   	} else if (is_gen12_ccs_plane(fb, plane)) {
>   		/* The AUX CCS surface must be page aligned */
>   		return (uint64_t)fb->strides[plane] *
>