[igt-dev] [PATCH i-g-t v2] tools/registers: Add missing registers relevant to debug PSR underruns

[José Roberto de Souza]

>From TGL+, there is no eDP transcoder instead all transcoders supports
eDP panels but in 99% of the cases it is used in pipe/transcoder A.
Also there is couple of new registers for PSR2 selective fetch.

v2:
- adding VIDEO DIP

Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
---
 tools/registers/icl_delta.txt       |  3 +++
 tools/registers/skl_display.txt     |  8 ++++++++
 tools/registers/tigerlake_delta.txt | 16 ++++++++++++++++
 3 files changed, 27 insertions(+)

diff --git a/tools/registers/icl_delta.txt b/tools/registers/icl_delta.txt
index 0323cfeaa..d7f086e61 100644
--- a/tools/registers/icl_delta.txt
+++ b/tools/registers/icl_delta.txt
@@ -214,6 +214,9 @@
 ('PLANE_WM_TRANS_5_C', '0x72468', '')
 ('PLANE_WM_TRANS_6_C', '0x72468', '')
 ('PLANE_WM_TRANS_7_C', '0x72468', '')
+('PIPE_STATUS_A', '0x70058', '')
+('PIPE_STATUS_B', '0x71058', '')
+('PIPE_STATUS_C', '0x72058', '')
 # TRANSCODER_DSI_DDI_CONTROL
 ('TRANS_DDI_FUNC_CTL_DSI0', '0x6b400', '')
 ('TRANS_DDI_FUNC_CTL_DSI1', '0x6bc00', '')
diff --git a/tools/registers/skl_display.txt b/tools/registers/skl_display.txt
index cb1a3e938..60e7aa996 100644
--- a/tools/registers/skl_display.txt
+++ b/tools/registers/skl_display.txt
@@ -404,3 +404,11 @@
 ('WM_LINETIME_B', '0x45274', '')
 ('WM_LINETIME_C', '0x45278', '')
 ('WM_MISC', '0x45260', '')
+# VIDEO DIP
+('VIDEO_DIP_CTL_A', '0x60200', '')
+('VIDEO_DIP_CTL_B', '0x61200', '')
+('VIDEO_DIP_CTL_C', '0x62200', '')
+
+# MISC
+('DC_STATE_EN', '0x45504', '')
+('DC_STATE_DEBUG', '0x45520', '')
diff --git a/tools/registers/tigerlake_delta.txt b/tools/registers/tigerlake_delta.txt
index c7fc2dc24..fbba14f7a 100644
--- a/tools/registers/tigerlake_delta.txt
+++ b/tools/registers/tigerlake_delta.txt
@@ -317,3 +317,19 @@
 # WATERMARK
 ('WM_LINETIME_D', '0x4527c', '')
 
+# PSR
+('TRANS_PSR_CTL_A',            '0x60800', '')
+('TRANS_PSR_STATUS_A',         '0x60840', '')
+('TRANS_PSR_EVENT_A',          '0x60848', '')
+('TRANS_PSR_MASK_A',           '0x60860', '')
+('TRANS_PSR2_CTL_A',           '0x60900', '')
+('TRANS_PSR2_MAN_TRK_CTL_A',   '0x60910', '')
+('TRANS_PSR2_STATUS_A',        '0x60940', '')
+('PLANE_SEL_FETCH_CTL_1_A',    '0x70890', '')
+('PLANE_SEL_FETCH_POS_1_A',    '0x70894', '')
+('PLANE_SEL_FETCH_SIZE_1_A',   '0x70898', '')
+('PLANE_SEL_FETCH_OFFSET_1_A', '0x7089C', '')
+
+# MISC
+('DMC_DEBUG_DC5_COUNT', '0x101084', '')
+('DMC_DEBUG_DC6_COUNT', '0x101088', '')
-- 
2.32.0