[igt-dev] [PATCH i-g-t 6/6] lib/i915: Add ADL-P plane offset restriction for CCS framebuffers
Matt Roper
matthew.d.roper at intel.com
Fri Jun 4 20:39:27 UTC 2021
From: Imre Deak <imre.deak at intel.com>
All DPT FB plane offsets must be 2MB-aligned. The kernel takes care of
aligning the offset for non-CCS framebuffers. Make sure that the
allocated CCS FB layout meets the alignment requirement.
Signed-off-by: Imre Deak <imre.deak at intel.com>
Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
lib/igt_fb.c | 26 ++++++++++++++++++++++++--
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/lib/igt_fb.c b/lib/igt_fb.c
index ce2aa6ce..ab52ea9f 100644
--- a/lib/igt_fb.c
+++ b/lib/igt_fb.c
@@ -804,11 +804,23 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
return (uint64_t) fb->strides[plane] *
ALIGN(fb->plane_height[plane], tile_height);
} else if (is_gen12_ccs_plane(fb, plane)) {
+ uint64_t size;
+
/* The AUX CCS surface must be page aligned */
- return (uint64_t)fb->strides[plane] *
+ size = (uint64_t)fb->strides[plane] *
ALIGN(fb->plane_height[plane], 64);
+
+ /*
+ * On ADL_P CCS color planes must be 2MB aligned, until remapping
+ * support is added for CCS FBs.
+ */
+ if (IS_ALDERLAKE_P(intel_get_drm_devid(fb->fd)))
+ size = ALIGN(size, 2 * 1024 * 1024);
+
+ return size;
} else {
unsigned int tile_width, tile_height;
+ uint64_t size;
igt_get_fb_tile_size(fb->fd, fb->modifier, fb->plane_bpp[plane],
&tile_width, &tile_height);
@@ -817,8 +829,18 @@ static uint64_t calc_plane_size(struct igt_fb *fb, int plane)
if (is_gen12_ccs_modifier(fb->modifier))
tile_height *= 4;
- return (uint64_t) fb->strides[plane] *
+ size = (uint64_t)fb->strides[plane] *
ALIGN(fb->plane_height[plane], tile_height);
+
+ /*
+ * On ADL_P CCS color planes must be 2MB aligned, until remapping
+ * support is added for CCS FBs.
+ */
+ if (IS_ALDERLAKE_P(intel_get_drm_devid(fb->fd)) &&
+ is_ccs_modifier(fb->modifier))
+ size = ALIGN(size, 2 * 1024 * 1024);
+
+ return size;
}
}
--
2.25.4
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