[igt-dev] [RFC i-g-t 04/11] Perform a regular 3d copy as a control checkpoint

[Chris Wilson]

Quoting Alan Previn (2021-03-02 22:53:27)
> As a control checkpoint, allocate buffers to be used
> as texture and render target in the 3d engine for a
> regular src to dest copy blit and verify buffer pixels.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis at intel.com>
> ---
>  tests/i915/i915_pxp.c | 181 ++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 181 insertions(+)
> 
> diff --git a/tests/i915/i915_pxp.c b/tests/i915/i915_pxp.c
> index 40a817b2..f12ca3d5 100644
> --- a/tests/i915/i915_pxp.c
> +++ b/tests/i915/i915_pxp.c
> @@ -28,6 +28,11 @@ IGT_TEST_DESCRIPTION("Test PXP (Protected Xe Path), which is the component "
>  #define CTX_MODIFY_PROTECTED_BOTHPARAMS_TO_INVALID 8
>  #define CTX_MODIFY_UNPROTECTED_BOTHPARAMS_TO_VALID 9
>  
> +/* test-configs for protected rendering operations */
> +#define COPY3D_BASELINE_SRC_TO_DST 1
> +#define COPY3D_PROTECTED_SRC_TO_PROTDST 2
> +#define COPY3D_PROTECTED_PROTSRC_TO_PROTDST 3
> +
>  static bool is_pxp_hw_supported(int i915)
>  {
>         uint32_t gen;
> @@ -333,10 +338,172 @@ static void test_create_protected_context(int i915, uint32_t test_cfg)
>         }
>  }
>  
> +static void fill_bo_content(int i915, uint32_t bo,
> +       uint32_t size, uint32_t initcolor)
> +{
> +       uint32_t *ptr, *ptrtmp;
> +       int loop = 0;
> +
> +       ptr = gem_mmap__cpu_coherent(i915, bo, 0,
> +                       size, PROT_WRITE);
> +       igt_assert(ptr);

Already done.

So the map here is in the WB, but the data may not be in the CPU cache
nor properly tracked as the buffer may not be cache coherent.

Same for the check.

Use gem_mmap__device_coherent() by default and cpu_coherent only when
you want to handle the cache coherency.
-Chris