[igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy

[Teres Alexis, Alan Previn]

Hi there Chris, 
WRT below review feedback: 
	"... just have the caller do 1-3 once for its protected context. Call it something like intel_bb_enable_pxp(), intel_bb_set_pxp if it should be reversible.",..

If we are thinking about having this new "intel_bb_set_pxp" function to dispatch the MI_SET_APPID and PIPE_CONTROL HW instructions out to HW at the time its called, it wouldn't work.  The reason for this is because the HW requires that enabling protected memory access and disabling protected memory access must be programmed in pairs within the same "dispatch of commands" to HW. I've tested and confirmed this. I was thinking about prepending and appending the ibb used by _gen9_render_op (at the point when it calls intel_bb_exec) but that doesn’t look scalable since the rendering code is manipulating the ibb pointers and splitting the batchbuffer bo to be used for both the 3d state as well as 3d instruction. It might be possible to create and chain batches at the time of intel_bb_exec depending on the pxp state but this would be a decent amount of re-write of the intel_batchbuffer init + cleanup code too. Are you okay with using the intel_bb_set_pxp to only mark the intended pxp state but still have the _gen9_render_op actually trigger those enable-disable instruction pairs?

...alan

-----Original Message-----
From: Chris Wilson <chris at chris-wilson.co.uk> 
Sent: Wednesday, March 3, 2021 3:56 PM
To: Teres Alexis, Alan Previn <alan.previn.teres.alexis at intel.com>; igt-dev at lists.freedesktop.org
Cc: Teres Alexis, Alan Previn <alan.previn.teres.alexis at intel.com>
Subject: Re: [igt-dev] [RFC i-g-t 06/11] Enable protected session and protected buffers in rendercopy

Quoting Alan Previn (2021-03-02 22:53:29)
> 1. In _gen9_render_op, check if the incoming batchbuffer
>    was marked with pxp enabled. If so, insert MI_SET_APPID
>    along with PIPE_CONTROL instructions at the start and
>    end of the rendering operation in the command buffer.
> 
> 2. The two PIPE_CONTROLs will enable protected memory
>    at the start of the batch and disabling protected
>    memory at the end of it. These PIPE_CONTROLs require a
>    Post-Sync operation with a write to memory.
> 
> 3. In order to satisfy #2, _gen9_render_op shall
>    allocate and pin a bo that is referenced by the
>    PIPE_CONTROL PostSync write to memory.

Or, just have the caller do 1-3 once for its protected context.
Call it something like intel_bb_enable_pxp(), intel_bb_set_pxp if it should be reversible.

> +       if (ibb->pxp.enabled) {
> +               gem_sync(ibb->i915, fenceb.handle);

No implicit syncs, ever. That will hide too may issues.
-Chris