[igt-dev] [PATCH i-g-t] tests/i915/gem_ctx_isolation.c - fix to poison CACHE_MODE_0

[Zbigniew Kempczyński]

From: CQ Tang <cq.tang at intel.com>

On DG2, if we poison bit8 of this register 0x7000, it causes the test
to catch "GPU hung". bit8 is "Depth Related Cache Pipelined Flush
Disable", set this to enable slow mode.
This change is to mask off to set bit8 of this register.

Signed-off-by: CQ Tang <cq.tang at intel.com>
Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
Cc: Chris P Wilson <chris.p.wilson at intel.com>
Cc: Kamil Konieczny <kamil.konieczny at linux.intel.com>
---
 tests/i915/gem_ctx_isolation.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tests/i915/gem_ctx_isolation.c b/tests/i915/gem_ctx_isolation.c
index bcb9b73410..95d13969fa 100644
--- a/tests/i915/gem_ctx_isolation.c
+++ b/tests/i915/gem_ctx_isolation.c
@@ -116,7 +116,13 @@ static const struct named_register {
 	{ "OACTXID", GEN8, RCS0, 0x2364 },
 	{ "PS_INVOCATION_COUNT_2", GEN8, RCS0, 0x2448, 2, .write_mask = ~0x3 },
 	{ "PS_DEPTH_COUNT_2", GEN8, RCS0, 0x2450, 2 },
-	{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true },
+	{ "Cache_Mode_0", GEN7, RCS0, 0x7000, .masked = true,
+	  /*
+	   * bit8 is "Depth Relate Cache Pipelined Flush Disable",
+	   * set this to enable slow mode, and the test catches
+	   * "GPU hung" on DG2, so mask off to poison this bit.
+	   */
+	  .write_mask = ~0x100 },
 	{ "Cache_Mode_1", GEN7, RCS0, 0x7004, .masked = true },
 	{ "GT_MODE", GEN8, RCS0, 0x7008, .masked = true },
 	{ "L3_Config", GEN_RANGE(8, 11), RCS0, 0x7034 },
-- 
2.32.0