[igt-dev] [PATCH i-g-t v6 01/13] lib/i915: memory region gtt_alignment support

[Niranjana Vishwanathapura]

Update library to include gtt_alignment field to support
platforms with 64K device memory pages.

v2: Do not pull in gtt_alignment uapi

Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
---
 lib/i915/intel_memory_region.c | 6 ++++++
 lib/i915/intel_memory_region.h | 1 +
 lib/intel_chipset.h            | 2 ++
 3 files changed, 9 insertions(+)

diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
index 84e1bceb3..964962ebb 100644
--- a/lib/i915/intel_memory_region.c
+++ b/lib/i915/intel_memory_region.c
@@ -948,6 +948,12 @@ struct gem_memory_region *__gem_get_memory_regions(int i915)
 		if (r->size == -1ull)
 			r->size = igt_get_avail_ram_mb() << 20;
 
+		if (HAS_64K_PAGES(intel_get_drm_devid(i915)) &&
+		    r->ci.memory_class == I915_MEMORY_CLASS_DEVICE)
+			r->gtt_alignment = 16 * PAGE_SIZE;
+		else
+			r->gtt_alignment = PAGE_SIZE;
+
 		asprintf(&r->name, "%s%d",
 			 region_repr(&r->ci), r->ci.memory_instance);
 
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
index 425bda0ec..84abb95b1 100644
--- a/lib/i915/intel_memory_region.h
+++ b/lib/i915/intel_memory_region.h
@@ -174,6 +174,7 @@ struct gem_memory_region {
 	char *name;
 
 	struct drm_i915_gem_memory_class_instance ci;
+	uint64_t gtt_alignment;
 	uint64_t size;
 	uint64_t cpu_size;
 };
diff --git a/lib/intel_chipset.h b/lib/intel_chipset.h
index d7a6ff190..7cf825915 100644
--- a/lib/intel_chipset.h
+++ b/lib/intel_chipset.h
@@ -225,4 +225,6 @@ void intel_check_pch(void);
 
 #define HAS_FLATCCS(devid)	(intel_get_device_info(devid)->has_flatccs)
 
+#define HAS_64K_PAGES(devid)	(IS_DG2(devid))
+
 #endif /* _INTEL_CHIPSET_H */
-- 
2.21.0.rc0.32.g243a4c7e27