[igt-dev] [PATCH] [i-g-t] tests/amdgpu/amd_link_settings: use mode 640x480 for link configuration test

[Wu, Hersen]

[AMD Official Use Only - General]

For DP bandwidth vs video timing, you please refer to https://en.wikipedia.org/wiki/DisplayPort

Here is rough calculation of video timing and DP lane bandwidth.

video mode timing needs bandwidth in bits:
pixel_clock x bit_per_color x 3

3840x2160 at 60hz pixel clock could be 594Mhz. For bits_per_color =8.
594x1,000,000 x 8 x 3 = 14,256 x 1,000,000


DP lane support bandwidth in bits. Be aware that 10 bits of DP lane (including control bit etc.) consists of 1 DP symbol (8bits).
20 percent of DP lane bandwidth is used for control, not for pixel data.

(link_rate X Lane_count) * (8 /10)

<1 Lane, 1.62GHz> DP lane:

((1 x 1.62 x 1,000,000,000) * (8 /10) = 1,296 x ,1000,1000




-----Original Message-----
From: Wu, Hersen 
Sent: Monday, April 24, 2023 3:09 PM
To: Siqueira, Rodrigo <Rodrigo.Siqueira at amd.com>; igt-dev at lists.freedesktop.org; Pillai, Aurabindo <Aurabindo.Pillai at amd.com>; Hung, Alex <Alex.Hung at amd.com>; Mahfooz, Hamza <Hamza.Mahfooz at amd.com>
Subject: RE: [PATCH] [i-g-t] tests/amdgpu/amd_link_settings: use mode 640x480 for link configuration test

[AMD Official Use Only - General]

Reply in-line.

-----Original Message-----
From: Siqueira, Rodrigo <Rodrigo.Siqueira at amd.com> 
Sent: Monday, April 24, 2023 12:46 PM
To: Wu, Hersen <hersenxs.wu at amd.com>; igt-dev at lists.freedesktop.org; Pillai, Aurabindo <Aurabindo.Pillai at amd.com>; Hung, Alex <Alex.Hung at amd.com>; Mahfooz, Hamza <Hamza.Mahfooz at amd.com>
Subject: Re: [PATCH] [i-g-t] tests/amdgpu/amd_link_settings: use mode 640x480 for link configuration test



On 4/24/23 08:16, Hersen Wu wrote:
> with 4k dp connected, amdgpu kernel warning mesaage dp_blank timeout

/mesaage/message/

> happens intermittently. link configuration <1, 162> could not support

Do you mean 1.62?

[Hersen] typos. Fix in review version2.

> 4k mode. dp safe mode 640x480 at 60hz could be used for all link

Is this safe mode defined in the spec?

[Hersen] DP safe mode is defined within DP specification and DP Link Layer Compliance Test Specification.

Also, after set to this safe mode this test stop to be intermittently?

{Hersen] Run 30 loops of test, the issue could not be reproduced.


> configuration test.
> 
> Signed-off-by: Hersen Wu <hersenxs.wu at amd.com>
> ---
>   tests/amdgpu/amd_link_settings.c | 25 ++++++++++++++++++++++++-
>   1 file changed, 24 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/amdgpu/amd_link_settings.c b/tests/amdgpu/amd_link_settings.c
> index 14c8c4d7..ec5e6fe5 100644
> --- a/tests/amdgpu/amd_link_settings.c
> +++ b/tests/amdgpu/amd_link_settings.c
> @@ -159,6 +159,24 @@ static void run_link_training_config(data_t *data, igt_output_t *output)
>   	}
>   }
>   
> +static const drmModeModeInfo dp_safe_mode_640_480 = {
> +	.name		= "640x480",
> +	.vrefresh	= 60,
> +	.clock		= 25200,
> +
> +	.hdisplay	= 640,
> +	.hsync_start	= 656,
> +	.hsync_end	= 752,
> +	.htotal		= 800,
> +
> +	.vdisplay	= 480,
> +	.vsync_start	= 490,
> +	.vsync_end	= 492,
> +	.vtotal		= 525,
> +
> +	.flags		= DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
> +};
> +
>   static void test_link_training_configs(data_t *data)
>   {
>   	const drmModeModeInfo *orig_mode;
> @@ -177,7 +195,12 @@ static void test_link_training_configs(data_t *data)
>   		/* Init only if display supports link_settings */
>   		test_init(data, output);
>   
> -		orig_mode = igt_output_get_mode(output);
> +		/* run_link_training_config run test from <1, 1.62>
> +		 * to highest link configuration. to make sure mode timing
> +		 * be fitted into <1, 1.62> and higher configuration, use
> +		 * dp safe mode 640x480 at 60hz
> +		 */
> +		orig_mode = &dp_safe_mode_640_480;
>   		igt_assert(orig_mode);
>   		igt_output_override_mode(output, orig_mode);
>