[PATCH i-g-t v5 4/6] lib/intel_blt: Update caching mode and pat_index

[Jahagirdar, Akshata]

-----Original Message-----
From: Auld, Matthew <matthew.auld at intel.com> 
Sent: Tuesday, December 12, 2023 1:25 AM
To: Jahagirdar, Akshata <akshata.jahagirdar at intel.com>
Cc: igt-dev at lists.freedesktop.org; Siddiqui, Ayaz A <ayaz.siddiqui at intel.com>; Stolarek, Karolina <karolina.stolarek at intel.com>; Kempczynski, Zbigniew <zbigniew.kempczynski at intel.com>; Mishra, Pallavi <pallavi.mishra at intel.com>; kamil.konieczny at linux.intel.com
Subject: Re: [PATCH i-g-t v5 4/6] lib/intel_blt: Update caching mode and pat_index

On 12/12/2023 17:39, Akshata Jahagirdar wrote:
> The pat-index and caching mode for compression need to change to 
> uc_comp in case of compression, else they just take the default value of pat_index and caching.
> 
> Signed-off-by: Akshata Jahagirdar <akshata.jahagirdar at intel.com>
> Acked-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
> ---
>   lib/intel_blt.c | 13 ++++++++++---
>   1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/lib/intel_blt.c b/lib/intel_blt.c index 
> 5399be20a..31b9f250e 100644
> --- a/lib/intel_blt.c
> +++ b/lib/intel_blt.c
> @@ -1797,7 +1797,8 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
>   	uint64_t size = width * height * bpp / 8;
>   	uint32_t stride = tiling == T_LINEAR ? width * 4 : width;
>   	uint32_t handle;
> -
> +	uint8_t pat_index = DEFAULT_PAT_INDEX;
> +	uint16_t cpu_caching;

Nit: newline here. Also maybe move cpu_caching into the xe specific path where it is used?

Reviewed-by: Matthew Auld <matthew.auld at intel.com>

AJ: Sounds good, will do.

>   	igt_assert_f(blt->driver, "Driver isn't set, have you called 
> blt_copy_init()?\n");
>   
>   	obj = calloc(1, sizeof(*obj));
> @@ -1810,14 +1811,20 @@ blt_create_object(const struct blt_copy_data *blt, uint32_t region,
>   		if (create_mapping && region != system_memory(blt->fd))
>   			flags |= DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM;
>   
> +		if (AT_LEAST_GEN(intel_get_drm_devid(blt->fd), 20) && compression) {
> +			pat_index = intel_get_pat_idx_uc_comp(blt->fd);
> +			cpu_caching = DRM_XE_GEM_CPU_CACHING_WC;
> +		} else
> +			cpu_caching = __xe_default_cpu_caching(blt->fd, region, flags);
> +
>   		size = ALIGN(size, xe_get_default_alignment(blt->fd));
> -		handle = xe_bo_create_flags(blt->fd, 0, size, region);
> +		handle = xe_bo_create_caching(blt->fd, 0, size, region, flags, 
> +cpu_caching);
>   	} else {
>   		igt_assert(__gem_create_in_memory_regions(blt->fd, &handle,
>   							  &size, region) == 0);
>   	}
>   
> -	blt_set_object(obj, handle, size, region, mocs_index, DEFAULT_PAT_INDEX, tiling,
> +	blt_set_object(obj, handle, size, region, mocs_index, pat_index, 
> +tiling,
>   		       compression, compression_type);
>   	blt_set_geom(obj, stride, 0, 0, width, height, 0, 0);
>