[igt-dev] [PATCH 2/4] lib/igt_sysfs: Handling gt related sysfs uapi changes.

[Ghimiray, Himal Prasad]

Hi Priyanka,

> -----Original Message-----
> From: Dandamudi, Priyanka <priyanka.dandamudi at intel.com>
> Sent: 20 June 2023 17:49
> To: Ghimiray, Himal Prasad <himal.prasad.ghimiray at intel.com>; igt-
> dev at lists.freedesktop.org
> Subject: RE: [igt-dev] [PATCH 2/4] lib/igt_sysfs: Handling gt related sysfs uapi
> changes.
> 
> 
> 
> > -----Original Message-----
> > From: igt-dev <igt-dev-bounces at lists.freedesktop.org> On Behalf Of
> > Himal Prasad Ghimiray
> > Sent: 13 June 2023 07:12 PM
> > To: igt-dev at lists.freedesktop.org
> > Subject: [igt-dev] [PATCH 2/4] lib/igt_sysfs: Handling gt related
> > sysfs uapi changes.
> >
> > Patch https://patchwork.freedesktop.org/series/118927/
> > is moving gt sysfs parent under tile folder.
> >
> > With the above patch path for sysfs changes:
> > from: /sys/class/drm/cardX/device/gtN/ to :
> > /sys/class/drm/cardX/device/tileN/gtN
> >
> > Adding xe_for_each_gt_under_each_tile macro to access new path.
> >
> > Cc: Francois Dugast <francois.dugast at intel.com>
> > Cc: Ashutosh Dixit <ashutosh.dixit at intel.com>
> > Cc: Matt Roper <matthew.d.roper at intel.com>
> > Signed-off-by: Himal Prasad Ghimiray <himal.prasad.ghimiray at intel.com>
> > ---
> >  lib/igt_sysfs.h | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/lib/igt_sysfs.h b/lib/igt_sysfs.h index
> > 2fb2303c..6c0ab617 100644
> > --- a/lib/igt_sysfs.h
> > +++ b/lib/igt_sysfs.h
> > @@ -78,6 +78,11 @@
> >
> >  #define xe_for_each_tile for_each_sysfs_tile_dirfd
> >
> > +/* FIXME: Need to revisit if GT indexing under TILE changes from KMD
> > +*/ #define xe_for_each_gt_under_each_tile(xe__, gt__, tile__) \
> > +	for (gt__ = 0, tile__ = 0 ; gt__ < xe_number_gt(xe__); \
> > +	     (xe_number_gt(xe__) == igt_sysfs_get_num_tiles(xe__)) ? ++gt__,
> > +++tile__ : ++gt__)
> > +
> It looks like for PVC, MTL and system memory(without device memory) the
> above logic works.
> If we have both system memory and device memory, will the above logic
> work?
I don't see any correlation between types of memory and this logic.
Current patch is applicable for platforms with support of multitile with one gt per tile and single tile with multiple gt. 
The logic needs to be revisited once we have platforms with multigt and multitile support.
> >  enum i915_attr_id {
> >  	RPS_ACT_FREQ_MHZ,
> >  	RPS_CUR_FREQ_MHZ,
> > --
> > 2.25.1