[igt-dev] [Intel-xe] [PATCH i-g-t v2 08/13] lib/intel_mocs: Add Xe2 mocs indexes

[Lucas De Marchi]

On Tue, Oct 03, 2023 at 09:31:30PM -0700, Matt Roper wrote:
>On Tue, Oct 03, 2023 at 08:10:18PM -0700, Lucas De Marchi wrote:
>> Add WB and UC mocs indexes for Xe2 architecture and later.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>>  lib/intel_mocs.c | 7 ++++++-
>>  1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/lib/intel_mocs.c b/lib/intel_mocs.c
>> index 6a4ec25e4..d9de16932 100644
>> --- a/lib/intel_mocs.c
>> +++ b/lib/intel_mocs.c
>> @@ -14,6 +14,8 @@
>>  #define MTL_MOCS_WB_IDX				10
>>  #define GEN12_MOCS_UC_IDX			3
>>  #define GEN12_MOCS_WB_IDX			2
>> +#define XE2_MOCS_UC_IDX				3
>> +#define XE2_MOCS_WB_IDX				1
>
>Wouldn't we want index 4 here (WB in both L3 and L4) rather than just
>L3?

I think we were always using the same index as used on the kernel side.

If we are going to use index 4 here, then we also need to update the
kernel side to actually program it. Right now we are doing:

	static const struct xe_mocs_entry xe2_mocs_table[] = {
		/* Defer to PAT */
		MOCS_ENTRY(0, XE2_L3_0_WB | L4_0_WB, 0),
		/* Cached L3 + L4 */
		MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0),
		/* Uncached L3, Cached L4 */
		MOCS_ENTRY(2, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0),
		/* Uncached L3 + L4 */
		MOCS_ENTRY(3, IG_PAT | XE2_L3_3_UC | L4_3_UC, 0),
	};


Lucas De Marchi