[PATCH i-g-t] tests/intel/xe_vm.c: Enforce explicit WB caching in bind-flag-invalid

[Matthew Auld]

On 23/04/2024 21:16, Jagmeet Randhawa wrote:
> Update the bind-flag-invalid test by replacing xe_bo_create
> with xe_bo_create_caching, which introduces an additional
> parameter for setting the CPU caching mode explicitly.
> The cpu_caching parameter is now set to DRM_XE_GEM_CPU_CACHING_WB,
> aligning the buffer object's caching policy with the Write-Back (WB)
> memory type expected by intel_get_pat_idx_wb. Previously,
> xe_bo_create relied on a default cpu_caching that may or
> may not have been compatible with intel_get_pat_idx_wb.
> 
> Suggested-by: Oak Zeng <oak.zeng at intel.com>
> Signed-off-by: Jagmeet Randhawa <jagmeet.randhawa at intel.com>
> ---
>   tests/intel/xe_vm.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/tests/intel/xe_vm.c b/tests/intel/xe_vm.c
> index 13cca2752..d40a6d76e 100644
> --- a/tests/intel/xe_vm.c
> +++ b/tests/intel/xe_vm.c
> @@ -1776,13 +1776,14 @@ static void bind_flag_invalid(int fd)
>   	uint32_t bo, bo_size = xe_get_default_alignment(fd);
>   	uint64_t addr = 0x1a0000;
>   	uint32_t vm;
> +	uint16_t cpu_caching = DRM_XE_GEM_CPU_CACHING_WB;
>   	struct drm_xe_vm_bind bind;
>   	struct drm_xe_sync sync[1] = {
>   		{ .type = DRM_XE_SYNC_TYPE_SYNCOBJ, .flags = DRM_XE_SYNC_FLAG_SIGNAL, },
>   	};
>   
>   	vm = xe_vm_create(fd, 0, 0);
> -	bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, 0), 0);
> +	bo = xe_bo_create_caching(fd, vm, bo_size, vram_if_possible(fd, 0), 0, cpu_caching);

I think this will now blow up on dgpu, if using VRAM. WC for cpu_caching 
is the only supported mode when mapping VRAM. I don't see anything wrong 
with the existing code though. xe_bo_create() will already handle such 
things for you, and intel_get_pat_idx_wb() is meant to be compatible 
with most things (exception is maybe display).

>   	sync[0].handle = syncobj_create(fd, 0);
>   
>   	memset(&bind, 0, sizeof(bind));