[PATCH i-g-t 4/7] lib/intel_bufops: Drop tilings restrictions

[Zbigniew Kempczyński]

On Thu, Apr 25, 2024 at 04:08:23PM +0300, Juha-Pekka Heikkila wrote:
> On 25.4.2024 13.47, Zbigniew Kempczyński wrote:
> > Different platforms supports different tilings so instead of asserting
> > on buffer creation path move responsibility of passing valid data
> > to the test. It can use intel_cmds_info to iterate over supported
> > tilings so this is better extendible and requires fewer changes.
> > 
> > Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
> > ---
> >   lib/intel_bufops.c | 3 ---
> >   1 file changed, 3 deletions(-)
> > 
> > diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
> > index 007ccdb953..b96275e485 100644
> > --- a/lib/intel_bufops.c
> > +++ b/lib/intel_bufops.c
> > @@ -898,9 +898,6 @@ static void __intel_buf_init(struct buf_ops *bops,
> >   	if (compression) {
> >   		igt_require(bops->intel_gen >= 9);
> > -		igt_assert(req_tiling == I915_TILING_Y ||
> > -			   req_tiling == I915_TILING_Yf ||
> > -			   req_tiling == I915_TILING_4);
> 
> I'm wondering if it would make sense to flip this assert around instead of
> removing it? I mean would check here will not arrive linear and x-tile? I
> didn't check but I assume this compression flag will not be enabled for xe2?

I'm using this path to create compressed on xe2 and render-copy works
fine on linear/x/4/64 there.

--
Zbigniew

> 
> /Juha-Pekka
> 
> >   		/*
> >   		 * On GEN12+ we align the main surface to 4 * 4 main surface
> >   		 * tiles, which is 64kB. These 16 tiles are mapped by 4 AUX
>