[PATCH i-g-t v2] lib/gpgpu_shader: Fix compilation warning and write dword shader

[Dominik Grzegorzek]

1) Fix src1_null macro definition to match platforms which are mentioned in
the comment above the declaration. (DG2+)

Fixes:
iga64 -Xauto-deps -Wall -p=12p71 lib/iga64_generated_codes.c.d/iga64_assembly_eot.12p71.asm
line 2.37: warning: Src1.Length should suffix src1 register (e.g. r10:4)
(W) send.gtwy (8|M0) null r112 null 0 0x02000000 {EOT}
                                    ^
2) Zero out r4 register in media block write message to prevent
   errors when the same register was used earlier in the shader.

v2: clear r4 before setting r5 (with small grfs the instruction also clears r5)

Signed-off-by: Dominik Grzegorzek <dominik.grzegorzek at intel.com>
Reviewed-by: Andrzej Hajda <andrzej.hajda at intel.com>
---
 lib/gpgpu_shader.c          |  4 ++--
 lib/iga64_generated_codes.c | 18 +++++++++++-------
 lib/iga64_macros.h          |  2 +-
 3 files changed, 14 insertions(+), 10 deletions(-)

diff --git a/lib/gpgpu_shader.c b/lib/gpgpu_shader.c
index 991455c49..80bad342a 100644
--- a/lib/gpgpu_shader.c
+++ b/lib/gpgpu_shader.c
@@ -281,6 +281,8 @@ void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
 			       uint32_t y_offset)
 {
 	emit_iga64_code(shdr, media_block_write, "				\n\
+	// Clear message header							\n\
+(W)	mov (16|M0)              r4.0<1>:ud    0x0:ud				\n\
 	// Payload								\n\
 (W)	mov (1|M0)               r5.0<1>:ud    ARG(3):ud			\n\
 (W)	mov (1|M0)               r5.1<1>:ud    ARG(4):ud			\n\
@@ -303,8 +305,6 @@ void gpgpu_shader__write_dword(struct gpgpu_shader *shdr, uint32_t value,
 	// Load r2.4-7 with tg id Y + ARG(1):ud					\n\
 (W)	mov (1|M0)               r2.1<1>:ud    r0.6<0;1,0>:ud			\n\
 (W)	add (1|M0)               r2.1<1>:ud    r2.1<0;1,0>:ud    ARG(1):ud	\n\
-	// payload setup							\n\
-(W)	mov (16|M0)              r4.0<1>:ud    0x0:ud				\n\
 	// Store X and Y block start (160:191 and 192:223)			\n\
 (W)	mov (2|M0)               r4.5<1>:ud    r2.0<2;2,1>:ud			\n\
 	// Store X and Y block max_size (224:231 and 232:239)			\n\
diff --git a/lib/iga64_generated_codes.c b/lib/iga64_generated_codes.c
index 6a08c4844..87270bb46 100644
--- a/lib/iga64_generated_codes.c
+++ b/lib/iga64_generated_codes.c
@@ -3,10 +3,11 @@
 
 #include "gpgpu_shader.h"
 
-#define MD5_SUM_IGA64_ASMS 2c503cbfbd7b3043e9a52188ae4da7a8
+#define MD5_SUM_IGA64_ASMS 96abf1aa2d0cc900ebba8203cefdd30c
 
 struct iga64_template const iga64_code_media_block_write[] = {
 	{ .gen_ver = 2000, .size = 56, .code = (const uint32_t []) {
+		0x80100061, 0x04054220, 0x00000000, 0x00000000,
 		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x05154220, 0x00000000, 0xc0ded004,
 		0x80000061, 0x05254220, 0x00000000, 0xc0ded005,
@@ -14,15 +15,15 @@ struct iga64_template const iga64_code_media_block_write[] = {
 		0x80000069, 0x02058220, 0x02000014, 0xc0ded000,
 		0x80000061, 0x02150220, 0x00000064, 0x00000000,
 		0x80001940, 0x02158220, 0x02000214, 0xc0ded001,
-		0x80100061, 0x04054220, 0x00000000, 0x00000000,
-		0x80041a61, 0x04550220, 0x00220205, 0x00000000,
+		0x80041961, 0x04550220, 0x00220205, 0x00000000,
 		0x80000061, 0x04754220, 0x00000000, 0xc0ded002,
 		0x80132031, 0x00000000, 0xd00e0494, 0x04000000,
 		0x80000001, 0x00010000, 0x20000000, 0x00000000,
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 1270, .size = 56, .code = (const uint32_t []) {
+	{ .gen_ver = 1270, .size = 60, .code = (const uint32_t []) {
+		0x80040061, 0x04054220, 0x00000000, 0x00000000,
 		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x05254220, 0x00000000, 0xc0ded004,
 		0x80000061, 0x05454220, 0x00000000, 0xc0ded005,
@@ -38,7 +39,8 @@ struct iga64_template const iga64_code_media_block_write[] = {
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 1260, .size = 52, .code = (const uint32_t []) {
+	{ .gen_ver = 1260, .size = 56, .code = (const uint32_t []) {
+		0x80100061, 0x04054220, 0x00000000, 0x00000000,
 		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x05154220, 0x00000000, 0xc0ded004,
 		0x80000061, 0x05254220, 0x00000000, 0xc0ded005,
@@ -53,7 +55,8 @@ struct iga64_template const iga64_code_media_block_write[] = {
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 1250, .size = 56, .code = (const uint32_t []) {
+	{ .gen_ver = 1250, .size = 60, .code = (const uint32_t []) {
+		0x80040061, 0x04054220, 0x00000000, 0x00000000,
 		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x05254220, 0x00000000, 0xc0ded004,
 		0x80000061, 0x05454220, 0x00000000, 0xc0ded005,
@@ -69,7 +72,8 @@ struct iga64_template const iga64_code_media_block_write[] = {
 		0x80000001, 0x00010000, 0x30000000, 0x00000000,
 		0x80000901, 0x00010000, 0x00000000, 0x00000000,
 	}},
-	{ .gen_ver = 0, .size = 52, .code = (const uint32_t []) {
+	{ .gen_ver = 0, .size = 56, .code = (const uint32_t []) {
+		0x80040061, 0x04054220, 0x00000000, 0x00000000,
 		0x80000061, 0x05054220, 0x00000000, 0xc0ded003,
 		0x80000061, 0x05254220, 0x00000000, 0xc0ded004,
 		0x80000061, 0x05454220, 0x00000000, 0xc0ded005,
diff --git a/lib/iga64_macros.h b/lib/iga64_macros.h
index f4ef5cb16..03cc726d4 100644
--- a/lib/iga64_macros.h
+++ b/lib/iga64_macros.h
@@ -7,7 +7,7 @@
 #define IGA64_MACROS_H
 
 /* send instruction for DG2+ requires 0 length in case src1 is null, BSpec: 47443 */
-#if GEN_VER < 1271
+#if GEN_VER <= 1250
 #define src1_null null
 #else
 #define src1_null null:0
-- 
2.34.1