[PATCH i-g-t] tests/intel/gem_spin_batch: RCS/CCS must share VM on DG2 due to w/a

[Cavitt, Jonathan]

-----Original Message-----
From: Nirmoy Das <nirmoy.das at linux.intel.com> 
Sent: Thursday, August 15, 2024 12:49 AM
To: Cavitt, Jonathan <jonathan.cavitt at intel.com>; igt-dev at lists.freedesktop.org
Cc: Gupta, saurabhg <saurabhg.gupta at intel.com>; Zuo, Alex <alex.zuo at intel.com>; Harrison, John C <john.c.harrison at intel.com>; Das, Nirmoy <nirmoy.das at intel.com>; chris.p.wilson at linux.intel.com
Subject: Re: [PATCH i-g-t] tests/intel/gem_spin_batch: RCS/CCS must share VM on DG2 due to w/a
> 
> 
> On 8/14/2024 8:33 PM, Jonathan Cavitt wrote:
> > On DG2, both the RCS and CCS engine contexts must use the same virtual
> > address space when running parallel, non-preemptible work.  Failure to
> > do so results in a GPU hang.
> >
> > Suggested-by: John Harrison <john.c.harrison at intel.com>
> > Signed-off-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
> > CC: Nirmoy Das <nirmoy.das at intel.com>
> > CC: Chris Wilson <chris.p.wilson at linux.intel.com>
> > ---
> >   tests/intel/gem_spin_batch.c | 20 +++++++++++++++++++-
> >   1 file changed, 19 insertions(+), 1 deletion(-)
> >
> > diff --git a/tests/intel/gem_spin_batch.c b/tests/intel/gem_spin_batch.c
> > index 682a062180..19b13f7334 100644
> > --- a/tests/intel/gem_spin_batch.c
> > +++ b/tests/intel/gem_spin_batch.c
> > @@ -24,6 +24,7 @@
> >   
> >   #include "i915/gem.h"
> >   #include "i915/gem_ring.h"
> > +#include "i915/gem_vm.h"
> >   #include "igt.h"
> >   /**
> >    * TEST: gem spin batch
> > @@ -179,9 +180,20 @@ static void spin_all(int i915, const intel_ctx_t *ctx, unsigned int flags)
> >   	const struct intel_execution_engine2 *e;
> >   	intel_ctx_cfg_t cfg = ctx->cfg;
> >   	struct igt_spin *spin, *n;
> > +	uint32_t shared_vm_id = 0;
> >   	uint64_t ahnd;
> >   	IGT_LIST_HEAD(list);
> >   
> > +	/*
> > +	 * Wa_14014494547:DG2
> 
> HSD talks about DG2 and MTL, is this somehow fixed in MTL ?

See the function skip_bad_engine

-Jonathan Cavitt

> 
> 
> Nirmoy
> 
> > +	 * Both the RCS and CCS engine contexts must use the same
> > +	 * virtual address space when running parallel,
> > +	 * non-preemptible work.  Failure to do so results in a
> > +	 * GPU hang.
> > +	 */
> > +	if (IS_DG2(intel_get_drm_devid(i915)))
> > +		shared_vm_id = gem_vm_create(i915);
> > +
> >   	for_each_ctx_cfg_engine(i915, &cfg, e) {
> >   		if (!gem_class_can_store_dword(i915, e->class))
> >   			continue;
> > @@ -192,8 +204,11 @@ static void spin_all(int i915, const intel_ctx_t *ctx, unsigned int flags)
> >   		if (skip_bad_engine(i915, e))
> >   			continue;
> >   
> > -		if (flags & PARALLEL_SPIN_NEW_CTX)
> > +		if (flags & PARALLEL_SPIN_NEW_CTX) {
> > +			if (shared_vm_id)
> > +				cfg.vm = shared_vm_id;
> >   			ctx = intel_ctx_create(i915, &cfg);
> > +		}
> >   		ahnd = get_reloc_ahnd(i915, ctx->id);
> >   
> >   		/* Prevent preemption so only one is allowed on each engine */
> > @@ -218,6 +233,9 @@ static void spin_all(int i915, const intel_ctx_t *ctx, unsigned int flags)
> >   		igt_spin_free(i915, spin);
> >   		put_ahnd(ahnd);
> >   	}
> > +
> > +	if (shared_vm_id)
> > +		gem_vm_destroy(i915, shared_vm_id);
> >   }
> >   
> >   static bool has_userptr(int fd)
>