[PATCH i-g-t 1/3] drm/fourcc: Import drm_fourcc header from commit 5151fa3 ("drm/fourcc: define Intel Xe2 related tile4 ccs modifiers")
Zbigniew Kempczyński
zbigniew.kempczynski at intel.com
Thu Aug 22 11:28:52 UTC 2024
On Thu, Aug 22, 2024 at 02:22:50PM +0300, Juha-Pekka Heikkila wrote:
> commit 5151fa35ae5979821d091b80096b4c790b187bac
> Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
> Date: Fri Aug 16 14:52:28 2024 +0300
>
> drm/fourcc: define Intel Xe2 related tile4 ccs modifiers
>
> Add Tile4 type ccs modifiers to indicate presence of compression on Xe2.
> Here is defined I915_FORMAT_MOD_4_TILED_LNL_CCS which is meant for
> integrated graphics with igpu related limitations
> Here is also defined I915_FORMAT_MOD_4_TILED_BMG_CCS which is meant
> for discrete graphics with dgpu related limitations
>
> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
--
Zbigniew
> ---
> include/drm-uapi/drm_fourcc.h | 57 +++++++++++++++++++++++++++++++----
> 1 file changed, 51 insertions(+), 6 deletions(-)
>
> diff --git a/include/drm-uapi/drm_fourcc.h b/include/drm-uapi/drm_fourcc.h
> index 6b6235f7a..78abd819f 100644
> --- a/include/drm-uapi/drm_fourcc.h
> +++ b/include/drm-uapi/drm_fourcc.h
> @@ -54,7 +54,7 @@ extern "C" {
> * Format modifiers may change any property of the buffer, including the number
> * of planes and/or the required allocation size. Format modifiers are
> * vendor-namespaced, and as such the relationship between a fourcc code and a
> - * modifier is specific to the modifer being used. For example, some modifiers
> + * modifier is specific to the modifier being used. For example, some modifiers
> * may preserve meaning - such as number of planes - from the fourcc code,
> * whereas others may not.
> *
> @@ -79,7 +79,7 @@ extern "C" {
> * format.
> * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
> * see modifiers as opaque tokens they can check for equality and intersect.
> - * These users musn't need to know to reason about the modifier value
> + * These users mustn't need to know to reason about the modifier value
> * (i.e. they are not expected to extract information out of the modifier).
> *
> * Vendors should document their modifier usage in as much detail as
> @@ -323,6 +323,8 @@ extern "C" {
> * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
> */
> #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
> +#define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
> +#define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
>
> /*
> * 2 plane YCbCr MSB aligned
> @@ -538,7 +540,7 @@ extern "C" {
> * This is a tiled layout using 4Kb tiles in row-major layout.
> * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
> * are arranged in four groups (two wide, two high) with column-major layout.
> - * Each group therefore consits out of four 256 byte units, which are also laid
> + * Each group therefore consists out of four 256 byte units, which are also laid
> * out as 2x2 column-major.
> * 256 byte units are made out of four 64 byte blocks of pixels, producing
> * either a square block or a 2:1 unit.
> @@ -700,6 +702,31 @@ extern "C" {
> */
> #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
>
> +/*
> + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
> + * on integrated graphics
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all compressible GEM objects.
> + */
> +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
> +
> +/*
> + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
> + * on discrete graphics
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all compressible GEM objects. The GEM object must be stored in
> + * contiguous memory with a size aligned to 64KB
> + */
> +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
> +
> /*
> * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
> *
> @@ -934,7 +961,7 @@ extern "C" {
> * which corresponds to the "generic" kind used for simple single-sample
> * uncompressed color formats on Fermi - Volta GPUs.
> */
> -static __inline__ __u64
> +static inline __u64
> drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> {
> if (!(modifier & 0x10) || (modifier & (0xff << 12)))
> @@ -1101,7 +1128,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> */
>
> /*
> - * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
> + * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
> * modifiers) denote the category for modifiers. Currently we have three
> * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
> * sixteen different categories.
> @@ -1417,7 +1444,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> * Amlogic FBC Memory Saving mode
> *
> * Indicates the storage is packed when pixel size is multiple of word
> - * boudaries, i.e. 8bit should be stored in this mode to save allocation
> + * boundaries, i.e. 8bit should be stored in this mode to save allocation
> * memory.
> *
> * This mode reduces body layout to 3072 bytes per 64x32 superblock with
> @@ -1474,6 +1501,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> #define AMD_FMT_MOD_TILE_VER_GFX10 2
> #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
> #define AMD_FMT_MOD_TILE_VER_GFX11 4
> +#define AMD_FMT_MOD_TILE_VER_GFX12 5
>
> /*
> * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
> @@ -1484,6 +1512,8 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> /*
> * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
> * GFX9 as canonical version.
> + *
> + * 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
> */
> #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
> #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
> @@ -1491,6 +1521,21 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
> #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
> #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
>
> +/* Gfx12 swizzle modes:
> + * 0 - LINEAR
> + * 1 - 256B_2D - 2D block dimensions
> + * 2 - 4KB_2D
> + * 3 - 64KB_2D
> + * 4 - 256KB_2D
> + * 5 - 4KB_3D - 3D block dimensions
> + * 6 - 64KB_3D
> + * 7 - 256KB_3D
> + */
> +#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
> +#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
> +#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
> +#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
> +
> #define AMD_FMT_MOD_DCC_BLOCK_64B 0
> #define AMD_FMT_MOD_DCC_BLOCK_128B 1
> #define AMD_FMT_MOD_DCC_BLOCK_256B 2
> --
> 2.45.2
>
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