[PATCH i-g-t v2] lib/rendercopy_gen9: Fix Xe2 missing pixels on non-modulo-16 surfaces

[Grzegorzek, Dominik]

On Thu, 2024-02-01 at 18:18 +0100, Zbigniew Kempczyński wrote:
> Missing setting Kernel0Enable bit results in lack of rasterization
> of right and bottom part of the surface. Fix this as kms tests depends
> on that.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
> Tested-by: Jouni Högander <jouni.hogander at intel.com>
> ---
> v2: set Kernel0Enable bit only on Xe2+ keeping older platforms intact
> 
> 
> 
> ---
>  lib/rendercopy_gen9.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
> index bdfd9be087..a4220d78da 100644
> --- a/lib/rendercopy_gen9.c
> +++ b/lib/rendercopy_gen9.c
> @@ -863,7 +863,10 @@ gen8_emit_ps(struct intel_bb *ibb, uint32_t kernel, bool fast_clear) {
>  	intel_bb_out(ibb, 0);
>  
>  	intel_bb_out(ibb, GEN7_3DSTATE_PS | (12-2));
> -	intel_bb_out(ibb, kernel);
> +	if (AT_LEAST_GEN(intel_get_drm_devid(ibb->fd), 20))
> +		intel_bb_out(ibb, kernel | 1);
> +	else
> +		intel_bb_out(ibb, kernel);
Agreed, this Kernel0Enable field does not even exist on platforms before Xe2.
The change is definetly needed and:
Reviewed-by: Dominik Grzegorzek <dominik.grzegorzek at intel.com>

Regards,
Dominik
>  	intel_bb_out(ibb, 0); /* kernel hi */
>  
>  	if (fast_clear)