[PATCH] Fix CAT error by adjusting prefetch size for Xe2

[Kamil Konieczny]

Hi,

On 2024-01-18 at 08:45:12 +0000, Matthew Auld wrote:
> On 17/01/2024 20:46, Jagmeet Randhawa wrote:

please add also i-g-t after PATCH, so with Matthew suggestion
it would look like:

[PATCH i-g-t] tests/intel/xe_exec_store: account for prefetch on Xe2

> > Due to batch pre-fetch being quite aggressive on Xe2, we need
> > an extra 4K page at the end of the batch to ensure HW doesn't
> > pre-fetch beyond the boundaries of the batch itself, hitting
> > an invalid ppGTT page, resulting in CAT errors. Fix this by
> > accounting for the xe_cs_prefetch_size() when calculating
> > the size of the batch.
> > 
> > Suggested-by: Matthew Auld <matthew.auld at intel.com>
> > Signed-off-by: Jagmeet Randhawa <jagmeet.randhawa at intel.com>
> 
> Commit title needs to have some kind of prefix like:
> "tests/intel/xe_exec_store".
> 
> If the entire thing is too long then shorten to something like:
> "tests/intel/xe_exec_store: account for prefetch".

I will merge this with this ^, adding also at end "on Xe2".

Regards,
Kamil

> 
> Otherwise,
> Reviewed-by: Matthew Auld <matthew.auld at intel.com>
> 
> > ---
> >   tests/intel/xe_exec_store.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/tests/intel/xe_exec_store.c b/tests/intel/xe_exec_store.c
> > index 2e4f57b47..bed118688 100644
> > --- a/tests/intel/xe_exec_store.c
> > +++ b/tests/intel/xe_exec_store.c
> > @@ -201,7 +201,7 @@ static void store_cachelines(int fd, struct drm_xe_engine_class_instance *eci,
> >   	uint32_t *batch_map;
> >   	size_t bo_size = 4096;
> > -	bo_size = ALIGN(bo_size, xe_get_default_alignment(fd));
> > +	bo_size = ALIGN(bo_size + xe_cs_prefetch_size(fd), xe_get_default_alignment(fd));
> >   	vm = xe_vm_create(fd, 0, 0);
> >   	ahnd = intel_allocator_open(fd, 0, INTEL_ALLOCATOR_SIMPLE);
> >   	exec_queues = xe_exec_queue_create(fd, vm, eci, 0);