[PATCH i-g-t 02/14] tests/intel/xe_oa: Add first tests
Umesh Nerlige Ramappa
umesh.nerlige.ramappa at intel.com
Mon Jul 1 19:47:45 UTC 2024
On Sun, Jun 30, 2024 at 07:52:57PM -0700, Ashutosh Dixit wrote:
>Add "xe-ref-count" and "sysctl-defaults" subtests.
>
>v2: Set INTEL_XE_DEVICE_MAX_SUBSLICES to 64 (value on PVC)
>
>Signed-off-by: Ashutosh Dixit <ashutosh.dixit at intel.com>
>---
> lib/xe/xe_oa.h | 2 +-
> tests/intel/xe_oa.c | 805 ++++++++++++++++++++++++++++++++++++++++++++
> tests/meson.build | 2 +
> 3 files changed, 808 insertions(+), 1 deletion(-)
> create mode 100644 tests/intel/xe_oa.c
>
>diff --git a/lib/xe/xe_oa.h b/lib/xe/xe_oa.h
>index f6f2768b00..27ebb4b217 100644
>--- a/lib/xe/xe_oa.h
>+++ b/lib/xe/xe_oa.h
>@@ -19,7 +19,7 @@ extern "C" {
> #define _DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b))
>
> #define INTEL_XE_DEVICE_MAX_SLICES (8)
>-#define INTEL_XE_DEVICE_MAX_SUBSLICES (32)
>+#define INTEL_XE_DEVICE_MAX_SUBSLICES (64) /* Maximum on XE_PVC */
> #define INTEL_XE_DEVICE_MAX_EUS_PER_SUBSLICE (16) /* Maximum on gfx12 */
>
> enum intel_xe_oa_format_name {
>diff --git a/tests/intel/xe_oa.c b/tests/intel/xe_oa.c
>new file mode 100644
>index 0000000000..2b5044b116
>--- /dev/null
>+++ b/tests/intel/xe_oa.c
>@@ -0,0 +1,805 @@
>+// SPDX-License-Identifier: MIT
>+/*
>+ * Copyright © 2024 Intel Corporation
>+ */
>+
>+#include <stdlib.h>
>+#include <stdio.h>
>+#include <string.h>
>+#include <fcntl.h>
>+#include <inttypes.h>
>+#include <errno.h>
>+#include <signal.h>
>+#include <sys/stat.h>
>+#include <sys/time.h>
>+#include <sys/times.h>
>+#include <sys/types.h>
>+#include <dirent.h>
>+#include <time.h>
>+#include <poll.h>
>+#include <math.h>
>+
>+#include "drm.h"
>+#include "igt.h"
>+#include "igt_device.h"
>+#include "igt_sysfs.h"
>+#include "xe/xe_ioctl.h"
>+#include "xe/xe_query.h"
>+#include "xe/xe_oa.h"
>+
>+/**
>+ * TEST: perf
>+ * Description: Test the Xe OA metrics streaming interface
>+ * Category: Core
>+ * Mega feature: Performance interface
>+ * Sub-category: Performance tests
>+ * Functionality: oa
>+ * Feature: xe streaming interface, oa
>+ * Test category: Perf
>+ */
>+
>+#define OA_MI_REPORT_PERF_COUNT ((0x28 << 23) | (4 - 2))
>+
>+#define OAREPORT_REASON_MASK 0x3f
>+#define OAREPORT_REASON_SHIFT 19
>+#define OAREPORT_REASON_TIMER (1<<0)
>+#define OAREPORT_REASON_INTERNAL (3<<1)
>+#define OAREPORT_REASON_CTX_SWITCH (1<<3)
>+#define OAREPORT_REASON_GO (1<<4)
>+#define OAREPORT_REASON_CLK_RATIO (1<<5)
>+
>+#define PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET (1 << 19)
>+#define PIPE_CONTROL_SYNC_GFDT (1 << 17)
>+#define PIPE_CONTROL_NO_WRITE (0 << 14)
>+#define PIPE_CONTROL_WRITE_IMMEDIATE (1 << 14)
>+#define PIPE_CONTROL_WRITE_DEPTH_COUNT (2 << 14)
>+#define PIPE_CONTROL_RENDER_TARGET_FLUSH (1 << 12)
>+#define PIPE_CONTROL_INSTRUCTION_INVALIDATE (1 << 11)
>+#define PIPE_CONTROL_ISP_DIS (1 << 9)
>+#define PIPE_CONTROL_INTERRUPT_ENABLE (1 << 8)
>+/* GT */
>+#define PIPE_CONTROL_DATA_CACHE_INVALIDATE (1 << 5)
>+#define PIPE_CONTROL_PPGTT_WRITE (0 << 2)
>+#define PIPE_CONTROL_GLOBAL_GTT_WRITE (1 << 2)
>+
>+#define MAX_OA_BUF_SIZE (16 * 1024 * 1024)
>+#define OA_BUFFER_SIZE MAX_OA_BUF_SIZE
>+
>+#define RING_FORCE_TO_NONPRIV_ADDRESS_MASK 0x03fffffc
>+/*
>+ * Engine specific registers defined as offsets from engine->mmio_base. For
>+ * these registers, OR bit[0] with 1 so we can add the mmio_base when running
>+ * engine specific test.
>+ */
>+#define MMIO_BASE_OFFSET 0x1
>+
>+#define OAG_OASTATUS (0xdafc)
>+#define OAG_PERF_COUNTER_B(idx) (0xDA94 + 4 * (idx))
>+#define OAG_OATAILPTR (0xdb04)
>+#define OAG_OATAILPTR_MASK 0xffffffc0
>+#define OAG_OABUFFER (0xdb08)
>+
>+#define XE_OA_MAX_SET_PROPERTIES 16
>+
>+#define ADD_PROPS(_head, _tail, _key, _value) \
>+ do { \
>+ igt_assert((_tail - _head) < (XE_OA_MAX_SET_PROPERTIES * 2)); \
>+ *_tail++ = DRM_XE_OA_PROPERTY_##_key; \
>+ *_tail++ = _value; \
>+ } while (0)
>+
>+struct accumulator {
>+#define MAX_RAW_OA_COUNTERS 62
>+ enum intel_xe_oa_format_name format;
>+
>+ uint64_t deltas[MAX_RAW_OA_COUNTERS];
>+};
>+
>+/* OA unit types */
>+enum {
>+ OAG,
>+ OAR,
>+ OAM,
>+
>+ MAX_OA_TYPE,
>+};
>+
>+struct oa_format {
>+ const char *name;
>+ size_t size;
>+ int a40_high_off; /* bytes */
>+ int a40_low_off;
>+ int n_a40;
>+ int a64_off;
>+ int n_a64;
>+ int a_off;
>+ int n_a;
>+ int first_a;
>+ int first_a40;
>+ int b_off;
>+ int n_b;
>+ int c_off;
>+ int n_c;
>+ int oa_type; /* of enum intel_xe_oa_format_name */
>+ bool report_hdr_64bit;
>+ int counter_select;
>+ int counter_size;
>+ int bc_report;
>+};
>+
>+static struct oa_format gen12_oa_formats[XE_OA_FORMAT_MAX] = {
>+ [XE_OA_FORMAT_A32u40_A4u32_B8_C8] = {
>+ "A32u40_A4u32_B8_C8", .size = 256,
>+ .a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
>+ .a_off = 144, .n_a = 4, .first_a = 32,
>+ .b_off = 192, .n_b = 8,
>+ .c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
>+ .counter_select = 5,
>+ },
>+};
>+
>+static struct oa_format dg2_oa_formats[XE_OA_FORMAT_MAX] = {
>+ [XE_OAR_FORMAT_A32u40_A4u32_B8_C8] = {
>+ "A32u40_A4u32_B8_C8", .size = 256,
>+ .a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
>+ .a_off = 144, .n_a = 4, .first_a = 32,
>+ .b_off = 192, .n_b = 8,
>+ .c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAR,
>+ .counter_select = 5,
>+ },
>+ /* This format has A36 and A37 interleaved with high bytes of some A
>+ * counters, so we will accumulate only subset of counters.
>+ */
>+ [XE_OA_FORMAT_A24u40_A14u32_B8_C8] = {
>+ "A24u40_A14u32_B8_C8", .size = 256,
>+ /* u40: A4 - A23 */
>+ .a40_high_off = 160, .a40_low_off = 16, .n_a40 = 20, .first_a40 = 4,
>+ /* u32: A0 - A3 */
>+ .a_off = 16, .n_a = 4,
>+ .b_off = 192, .n_b = 8,
>+ .c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
>+ .counter_select = 5,
>+ },
>+ /* This format has 24 u64 counters ranging from A0 - A35. Until we come
>+ * up with a better mechanism to define missing counters, we will use a
>+ * subset of counters that are indexed by one-increments - A28 - A35.
>+ */
>+ [XE_OAC_FORMAT_A24u64_B8_C8] = {
>+ "OAC_A24u64_B8_C8", .size = 320,
>+ .a64_off = 160, .n_a64 = 8,
>+ .b_off = 224, .n_b = 8,
>+ .c_off = 256, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 1, },
>+};
>+
>+static struct oa_format mtl_oa_formats[XE_OA_FORMAT_MAX] = {
>+ [XE_OAR_FORMAT_A32u40_A4u32_B8_C8] = {
>+ "A32u40_A4u32_B8_C8", .size = 256,
>+ .a40_high_off = 160, .a40_low_off = 16, .n_a40 = 32,
>+ .a_off = 144, .n_a = 4, .first_a = 32,
>+ .b_off = 192, .n_b = 8,
>+ .c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAR,
>+ .counter_select = 5,
>+ },
>+ /* This format has A36 and A37 interleaved with high bytes of some A
>+ * counters, so we will accumulate only subset of counters.
>+ */
>+ [XE_OA_FORMAT_A24u40_A14u32_B8_C8] = {
>+ "A24u40_A14u32_B8_C8", .size = 256,
>+ /* u40: A4 - A23 */
>+ .a40_high_off = 160, .a40_low_off = 16, .n_a40 = 20, .first_a40 = 4,
>+ /* u32: A0 - A3 */
>+ .a_off = 16, .n_a = 4,
>+ .b_off = 192, .n_b = 8,
>+ .c_off = 224, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAG,
>+ .counter_select = 5,
>+ },
>+
>+ /* Treat MPEC countes as A counters for now */
>+ [XE_OAM_FORMAT_MPEC8u64_B8_C8] = {
>+ "MPEC8u64_B8_C8", .size = 192,
>+ .a64_off = 32, .n_a64 = 8,
>+ .b_off = 96, .n_b = 8,
>+ .c_off = 128, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAM_MPEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 1,
>+ },
>+ [XE_OAM_FORMAT_MPEC8u32_B8_C8] = {
>+ "MPEC8u32_B8_C8", .size = 128,
>+ .a_off = 32, .n_a = 8,
>+ .b_off = 64, .n_b = 8,
>+ .c_off = 96, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAM_MPEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 2,
>+ },
>+ /* This format has 24 u64 counters ranging from A0 - A35. Until we come
>+ * up with a better mechanism to define missing counters, we will use a
>+ * subset of counters that are indexed by one-increments - A28 - A35.
>+ */
>+ [XE_OAC_FORMAT_A24u64_B8_C8] = {
>+ "OAC_A24u64_B8_C8", .size = 320,
>+ .a64_off = 160, .n_a64 = 8,
>+ .b_off = 224, .n_b = 8,
>+ .c_off = 256, .n_c = 8, .oa_type = DRM_XE_OA_FMT_TYPE_OAC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 1, },
>+};
>+
>+static struct oa_format lnl_oa_formats[XE_OA_FORMAT_MAX] = {
>+ [XE_OA_FORMAT_PEC64u64] = {
>+ "PEC64u64", .size = 576,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 1,
>+ .counter_size = 1,
>+ .bc_report = 0 },
>+ [XE_OA_FORMAT_PEC64u64_B8_C8] = {
>+ "PEC64u64_B8_C8", .size = 640,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 1,
>+ .counter_size = 1,
>+ .bc_report = 1 },
>+ [XE_OA_FORMAT_PEC64u32] = {
>+ "PEC64u32", .size = 320,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 1,
>+ .counter_size = 0,
>+ .bc_report = 0 },
>+ [XE_OA_FORMAT_PEC32u64_G1] = {
>+ "PEC32u64_G1", .size = 320,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 5,
>+ .counter_size = 1,
>+ .bc_report = 0 },
>+ [XE_OA_FORMAT_PEC32u32_G1] = {
>+ "PEC32u32_G1", .size = 192,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 5,
>+ .counter_size = 0,
>+ .bc_report = 0 },
>+ [XE_OA_FORMAT_PEC32u64_G2] = {
>+ "PEC32u64_G2", .size = 320,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 6,
>+ .counter_size = 1,
>+ .bc_report = 0 },
>+ [XE_OA_FORMAT_PEC32u32_G2] = {
>+ "PEC32u64_G2", .size = 192,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 6,
>+ .counter_size = 0,
>+ .bc_report = 0 },
>+ [XE_OA_FORMAT_PEC36u64_G1_32_G2_4] = {
>+ "PEC36u64_G1_32_G2_4", .size = 320,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 3,
>+ .counter_size = 1,
>+ .bc_report = 0 },
>+ [XE_OA_FORMAT_PEC36u64_G1_4_G2_32] = {
>+ "PEC36u64_G1_4_G2_32_G2", .size = 320,
>+ .oa_type = DRM_XE_OA_FMT_TYPE_PEC,
>+ .report_hdr_64bit = true,
>+ .counter_select = 4,
>+ .counter_size = 1,
>+ .bc_report = 0 },
>+};
I think we should do away with the per platform arrays and instead do
something similar to what the KMD does - have a platform mask or
something because really the same format does not have a new definition
for another platform. It should just indicate what platforms the format
is supported on. Maybe please create an issue to track this and we can
look at it later sometime.
Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
Umesh
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