[PATCH i-g-t v2 07/10] tests/intel/xe_drm_fdinfo: Add an iterator for virtual engines

[Lucas De Marchi]

On Thu, Jul 11, 2024 at 11:31:37AM GMT, Umesh Nerlige Ramappa wrote:
>On Thu, Jul 11, 2024 at 08:34:03AM -0500, Lucas De Marchi wrote:
>>On Tue, Jul 02, 2024 at 05:25:29PM GMT, Umesh Nerlige Ramappa wrote:
>>>Add a helper iterator for virtual engines.
>>>
>>>Signed-off-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa at intel.com>
>>>---
>>>tests/intel/xe_drm_fdinfo.c | 29 +++++++++++++++++++++++++++++
>>>1 file changed, 29 insertions(+)
>>>
>>>diff --git a/tests/intel/xe_drm_fdinfo.c b/tests/intel/xe_drm_fdinfo.c
>>>index f2051c422..9d3d1b285 100644
>>>--- a/tests/intel/xe_drm_fdinfo.c
>>>+++ b/tests/intel/xe_drm_fdinfo.c
>>>@@ -90,6 +90,34 @@ static const uint64_t batch_addr[] = {
>>>	0x1d0000,
>>>	0x1e0000,
>>>};
>>>+
>>>+#define MAX_GTS 2
>>>+#define MAX_INSTANCE 9
>>>+struct virtual_hwe {
>>>+	struct drm_xe_engine_class_instance eci[MAX_INSTANCE];
>>>+	int count;
>>>+} vhwe[MAX_GTS][DRM_XE_ENGINE_CLASS_COMPUTE + 1] = {};
>>
>>there's no concept of "virtual engine". I think this is something
>>brought over from i915? Is it related to the width when submitting?
>>
>>Please add a comment for the confused reader and it's probably worth
>>this abstraction to be outside this test. +Matt Brost
>
>width is for parallel submission and num_placements is for virtual.

ok... let's also s/virtual engines/virtual exec_queues/  where
appropriate. Like we have in xe_exec_balancer.c

can we also use the helper in xe_exec_balancer?


Lucas De Marchi

>
>>
>>>+
>>>+static void list_virtual_engines(int fd)
>>
>>list? shouldn't it be virtual_engines_init()?
>
>Right, I will change that.
>
>Thanks,
>Umesh
>
>>
>>Lucas De Marchi
>>
>>>+{
>>>+	struct drm_xe_engine_class_instance *hwe;
>>>+
>>>+	xe_for_each_engine(fd, hwe) {
>>>+		struct virtual_hwe *v;
>>>+
>>>+		igt_assert(hwe->gt_id < MAX_GTS);
>>>+		igt_assert(hwe->engine_class < DRM_XE_ENGINE_CLASS_COMPUTE + 1);
>>>+		v = &vhwe[hwe->gt_id][hwe->engine_class];
>>>+
>>>+		igt_assert(v->count < MAX_INSTANCE);
>>>+		v->eci[v->count++] = *hwe;
>>>+	}
>>>+}
>>>+#define xe_for_each_multi_engine(__fd, __hwe, __count) \
>>>+	for (int igt_unique(gt) = 0; igt_unique(gt) < MAX_GTS; igt_unique(gt)++) \
>>>+		for (int igt_unique(c) = 0; igt_unique(c) < DRM_XE_ENGINE_CLASS_COMPUTE + 1; igt_unique(c)++) \
>>>+			for_if((__hwe = &vhwe[igt_unique(gt)][igt_unique(c)].eci[0]) && ((__count = vhwe[igt_unique(gt)][igt_unique(c)].count) > 1))
>>>+
>>>static void read_engine_cycles(int xe, struct pceu_cycles *pceu)
>>>{
>>>	struct drm_client_fdinfo info = { };
>>>@@ -678,6 +706,7 @@ igt_main
>>>		xe = drm_open_driver(DRIVER_XE);
>>>		igt_require_xe(xe);
>>>		igt_require(igt_parse_drm_fdinfo(xe, &info, NULL, 0, NULL, 0));
>>>+		list_virtual_engines(xe);
>>>	}
>>>
>>>	igt_describe("Check if basic fdinfo content is present for memory");
>>>-- 
>>>2.38.1
>>>