[PATCH i-g-t 1/3] tests/intel/kms_pm_dc:Add basic validation checks to achieve deep-pkgc

[Naladala Ramanaidu]

Add connector checks and test requirement validations for deep-pkgc

v2: Correct indentation and update comments (Suraj, Jeevan)

Signed-off-by: Naladala Ramanaidu <ramanaidu.naladala at intel.com>
---
 tests/intel/kms_pm_dc.c | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/tests/intel/kms_pm_dc.c b/tests/intel/kms_pm_dc.c
index e1318bfa6..8fb35a2df 100644
--- a/tests/intel/kms_pm_dc.c
+++ b/tests/intel/kms_pm_dc.c
@@ -592,31 +592,43 @@ static unsigned int read_pkgc_counter(int debugfs_root_fd)
 static void test_deep_pkgc_state(data_t *data)
 {
 	unsigned int pre_val = 0, cur_val = 0;
-	time_t start = time(NULL), duration = 2, delay;
+	time_t start = time(NULL), duration = 2, vb_delay, delay;
 	enum pipe pipe;
 	bool pkgc_flag = false;
-	bool vrr_supported = false, flip = true;
+	bool flip = true;
 
 	igt_display_t *display = &data->display;
 	igt_plane_t *primary;
 	igt_output_t *output = NULL;
 
 	for_each_pipe_with_valid_output(display, pipe, output) {
-		/* Check VRR capabilities before setting up */
+
+		if (output->config.connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+			igt_skip("No eDP output found, skipping the test.\n");
+		/* DEEP PKG_C_LATENCY can be configured only for fixed refresh rates */
 		if (igt_output_has_prop(output, IGT_CONNECTOR_VRR_CAPABLE) &&
 		    igt_output_get_prop(output, IGT_CONNECTOR_VRR_CAPABLE)) {
-			vrr_supported = true;
+			igt_pipe_set_prop_value(display, pipe,
+						IGT_CRTC_VRR_ENABLED, false);
+			igt_assert(igt_display_try_commit_atomic(display,
+								 DRM_MODE_ATOMIC_ALLOW_MODESET,
+								 NULL) == 0);
 			break;
 		}
 	}
 
-	/* Skip the test if no VRR capable output is found */
-	if (!vrr_supported)
-		igt_skip("No VRR capable output found, skipping the test.\n");
-
 	igt_display_reset(display);
-
 	igt_output_set_pipe(output, pipe);
+	for_each_connector_mode(output) {
+		data->mode = &output->config.connector->modes[j__];
+		vb_delay = 1 * (MSECS / (data->mode->vrefresh));
+		/*
+		 * At least 5ms vblank time required to program higher
+		 * watermark levels
+		 */
+		if (vb_delay > (5 * MSEC))
+			break;
+	}
 
 	data->output = output;
 	data->mode = igt_output_get_mode(output);
-- 
2.43.0