[PATCH i-g-t 1/2] drm-uapi/xe: Sync with topology query uapi updates

[Cavitt, Jonathan]

-----Original Message-----
From: igt-dev <igt-dev-bounces at lists.freedesktop.org> On Behalf Of Lucas De Marchi
Sent: Friday, July 19, 2024 6:28 AM
To: igt-dev at lists.freedesktop.org
Cc: De Marchi, Lucas <lucas.demarchi at intel.com>
Subject: [PATCH i-g-t 1/2] drm-uapi/xe: Sync with topology query uapi updates
> 
> Align with kernel commit 7108b4a589cd ("drm/xe/uapi: Expose SIMD16 EU
> mask in topology query") which adds one item to topology query.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

Aside from adding the DRM_XE_TOPO_SIMD16_EU_PER_DSS mask
type, seems to be mostly a change to the various comments.  No
complaints.

Reviewed-by: Jonathan Cavitt <jonathan.cavitt at intel.com>
-Jonathan Cavitt

> ---
>  include/drm-uapi/xe_drm.h | 26 ++++++++++++++++++++------
>  1 file changed, 20 insertions(+), 6 deletions(-)
> 
> diff --git a/include/drm-uapi/xe_drm.h b/include/drm-uapi/xe_drm.h
> index 3bab3fdaa..29425d7fd 100644
> --- a/include/drm-uapi/xe_drm.h
> +++ b/include/drm-uapi/xe_drm.h
> @@ -3,8 +3,8 @@
>   * Copyright © 2023 Intel Corporation
>   */
>  
> -#ifndef _XE_DRM_H_
> -#define _XE_DRM_H_
> +#ifndef _UAPI_XE_DRM_H_
> +#define _UAPI_XE_DRM_H_
>  
>  #include "drm.h"
>  
> @@ -134,7 +134,7 @@ extern "C" {
>   * redefine the interface more easily than an ever growing struct of
>   * increasing complexity, and for large parts of that interface to be
>   * entirely optional. The downside is more pointer chasing; chasing across
> - * the boundary with pointers encapsulated inside u64.
> + * the __user boundary with pointers encapsulated inside u64.
>   *
>   * Example chaining:
>   *
> @@ -517,7 +517,14 @@ struct drm_xe_query_gt_list {
>   *    available per Dual Sub Slices (DSS). For example a query response
>   *    containing the following in mask:
>   *    ``EU_PER_DSS    ff ff 00 00 00 00 00 00``
> - *    means each DSS has 16 EU.
> + *    means each DSS has 16 SIMD8 EUs. This type may be omitted if device
> + *    doesn't have SIMD8 EUs.
> + *  - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
> + *    Units (EU) available per Dual Sub Slices (DSS). For example a query
> + *    response containing the following in mask:
> + *    ``SIMD16_EU_PER_DSS    ff ff 00 00 00 00 00 00``
> + *    means each DSS has 16 SIMD16 EUs. This type may be omitted if device
> + *    doesn't have SIMD16 EUs.
>   */
>  struct drm_xe_query_topology_mask {
>  	/** @gt_id: GT ID the mask is associated with */
> @@ -527,6 +534,7 @@ struct drm_xe_query_topology_mask {
>  #define DRM_XE_TOPO_DSS_COMPUTE		2
>  #define DRM_XE_TOPO_L3_BANK		3
>  #define DRM_XE_TOPO_EU_PER_DSS		4
> +#define DRM_XE_TOPO_SIMD16_EU_PER_DSS	5
>  	/** @type: type of mask */
>  	__u16 type;
>  
> @@ -783,7 +791,13 @@ struct drm_xe_gem_create {
>  #define DRM_XE_GEM_CPU_CACHING_WC                      2
>  	/**
>  	 * @cpu_caching: The CPU caching mode to select for this object. If
> -	 * mmaping the object the mode selected here will also be used.
> +	 * mmaping the object the mode selected here will also be used. The
> +	 * exception is when mapping system memory (including data evicted
> +	 * to system) on discrete GPUs. The caching mode selected will
> +	 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
> +	 * between GPU- and CPU is guaranteed. The caching mode of
> +	 * existing CPU-mappings will be updated transparently to
> +	 * user-space clients.
>  	 */
>  	__u16 cpu_caching;
>  	/** @pad: MBZ */
> @@ -1684,4 +1698,4 @@ struct drm_xe_oa_stream_info {
>  }
>  #endif
>  
> -#endif /* _XE_DRM_H_ */
> +#endif /* _UAPI_XE_DRM_H_ */
> -- 
> 2.43.0
> 
>