[PATCH 2/2] tests/intel/kms_flip_scaled_crc: Add support for RGB16161616_64B compressed formats

[Kamil Konieczny]

Hi Melanie,
On 2024-06-06 at 17:45:23 +0530, Melanie Lobo wrote:

imho subject should be:

[PATCH 2/2] tests/intel/kms_flip_scaled_crc: Add tests for RGB16161616_64B compressed formats

There are also whitespaces error, please use checkpatch.pl
before sending (see CONTRIBUTING.md)

> MTL supports RGB FP16 format which is a binary floating-point computer
> number format that occupies 16 bits in computer memory. In this test
> platform shall render compression in display engine to receive
> RGB FP16 compressed formats.
> 
> This was tested with kernel patch,
> https://patchwork.freedesktop.org/series/124957/
> https://lore.kernel.org/all/20240605055819.9510-1-melanie.lobo@intel.com/
> 
> cc: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
> cc: Bhanuprakash Modem <bhanuprakash.modem at intel.com>
> cc: Swati Sharma <swati2.sharma at intel.com>
> Signed-off-by: Melanie Lobo <melanie.lobo at intel.com>
> ---
>  tests/intel/kms_flip_scaled_crc.c | 42 +++++++++++++++++++++++++++++++
>  1 file changed, 42 insertions(+)
> 
> diff --git a/tests/intel/kms_flip_scaled_crc.c b/tests/intel/kms_flip_scaled_crc.c
> index 7dc07bc8330d..65fd31c5c963 100644
> --- a/tests/intel/kms_flip_scaled_crc.c
> +++ b/tests/intel/kms_flip_scaled_crc.c
> @@ -96,6 +96,16 @@
>   * Description: Flip from 64bpp non scaled fb to 32bpp %arg[1] fb to stress CD
>   *              clock programming
>   *
> + * SUBTEST: flip-64bpp-4tile-to-32bpp-4tilemtlrcccsxrgb-%s
> + * Description: Flip from 64bpp non scaled fb to 32bpp %arg[1] fb to stress CD
> + * 		clock programming
-----^^^^^^^
Use tabs, then spaces.

> + * Functionality: ccs, scaling, tiling, vblank
> + *
> + * SUBTEST: flip-64bpp-4tile-to-32bpp-4tilemtlrcccsargb-%s
> + * Description: Flip from 64bpp non scaled fb to 32bpp %arg[1] fb to stress CD
> + * 		clock programming

Same here.

Regards,
Kamil

> + * Functionality: ccs, scaling, tiling, vblank
> + *
>   * arg[1]:
>   *
>   * @downscaling:        Downscaled
> @@ -345,6 +355,22 @@ const struct {
>  		1.0,
>  		2.0,
>  	},
> +	{
> +		"flip-64bpp-4tile-to-32bpp-4tilemtlrcccsxrgb-downscaling",
> +		"Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
> +		I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
> +		I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
> +		1.0,
> +		2.0,
> +	},
> +	{
> +		"flip-64bpp-4tile-to-32bpp-4tilemtlrcccsargb-downscaling",
> +		"Flip from 64bpp non scaled fb to 32bpp downscaled fb to stress CD clock programming",
> +		I915_FORMAT_MOD_4_TILED, DRM_FORMAT_ARGB16161616F,
> +		I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_ARGB16161616F,
> +		1.0,
> +		2.0,
> +	},
>  	{
>  		"flip-32bpp-ytile-to-64bpp-ytile-upscaling",
>  		"Flip from 32bpp non scaled fb to 64bpp upscaled fb to stress CD clock programming",
> @@ -529,6 +555,22 @@ const struct {
>  		0.5,
>  		1.0,
>  	},
> +	{
> +		"flip-64bpp-4tile-to-32bpp-4tilemtlrcccsxrgb-upscaling",
> +		"Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
> +		I915_FORMAT_MOD_4_TILED, DRM_FORMAT_XRGB16161616F,
> +		I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_XRGB16161616F,
> +		0.5,
> +		1.0,
> +	},
> +	{
> +		"flip-64bpp-4tile-to-32bpp-4tilemtlrcccsargb-upscaling",
> +		"Flip from 64bpp non scaled fb to 32bpp upscaled fb to stress CD clock programming",
> +		I915_FORMAT_MOD_4_TILED, DRM_FORMAT_ARGB16161616F,
> +		I915_FORMAT_MOD_4_TILED_MTL_RC_CCS, DRM_FORMAT_ARGB16161616F,
> +		0.5,
> +		1.0,
> +	},
>  };
>  
>  static void setup_fb(data_t *data, struct igt_fb *newfb, uint32_t width,
> -- 
> 2.17.1
>