[PATCH i-g-t v2] tests/api_intel_bb: Fix render-ccs subtest hang on DG2

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>

On 19.6.2024 8.18, Zbigniew Kempczyński wrote:
> Avoid hang by use appropriate compression tiling (Tile4) on DG2.
> Compressed surfaces also need to reside in vram for discrete so
> adjust this placement either.
> 
> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10380
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
> Cc: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
> ---
>   tests/intel/api_intel_bb.c | 40 ++++++++++++++++++++++++--------------
>   1 file changed, 25 insertions(+), 15 deletions(-)
> 
> diff --git a/tests/intel/api_intel_bb.c b/tests/intel/api_intel_bb.c
> index 4158fa06c8..6cb5d4f9e9 100644
> --- a/tests/intel/api_intel_bb.c
> +++ b/tests/intel/api_intel_bb.c
> @@ -849,10 +849,15 @@ static void scratch_buf_init(struct buf_ops *bops,
>   			     uint32_t req_tiling,
>   			     enum i915_compression compression)
>   {
> +	int fd = buf_ops_get_fd(bops);
>   	int bpp = 32;
> +	uint32_t region = REGION_SMEM;
>   
> -	intel_buf_init(bops, buf, width, height, bpp, 0,
> -		       req_tiling, compression);
> +	if (compression && gem_has_lmem(fd))
> +		region = REGION_LMEM(0);
> +
> +	intel_buf_init_in_region(bops, buf, width, height, bpp, 0,
> +				 req_tiling, compression, region);
>   
>   	igt_assert(intel_buf_width(buf) == width);
>   	igt_assert(intel_buf_height(buf) == height);
> @@ -1419,6 +1424,7 @@ static void render_ccs(struct buf_ops *bops)
>   	uint32_t compressed = 0;
>   	uint32_t devid = intel_get_drm_devid(i915);
>   	igt_render_copyfunc_t render_copy = NULL;
> +	int tiling = IS_DG2(devid) ? I915_TILING_4 : I915_TILING_Y;
>   
>   	ibb = intel_bb_create(i915, PAGE_SIZE);
>   	if (debug_bb)
> @@ -1426,9 +1432,9 @@ static void render_ccs(struct buf_ops *bops)
>   
>   	scratch_buf_init(bops, &src, width, height, I915_TILING_NONE,
>   			 I915_COMPRESSION_NONE);
> -	scratch_buf_init(bops, &dst, width, height, I915_TILING_Y,
> +	scratch_buf_init(bops, &dst, width, height, tiling,
>   			 I915_COMPRESSION_RENDER);
> -	scratch_buf_init(bops, &dst2, width, height, I915_TILING_Y,
> +	scratch_buf_init(bops, &dst2, width, height, tiling,
>   			 I915_COMPRESSION_RENDER);
>   	scratch_buf_init(bops, &final, width, height, I915_TILING_NONE,
>   			 I915_COMPRESSION_NONE);
> @@ -1459,21 +1465,25 @@ static void render_ccs(struct buf_ops *bops)
>   		    0, 0);
>   
>   	intel_bb_sync(ibb);
> -
> -	fails = compare_bufs(&src, &final, true);
> -	compressed = count_compressed(ibb->gen, &dst);
> -
>   	intel_bb_destroy(ibb);
>   
> -	igt_debug("fails: %u, compressed: %u\n", fails, compressed);
> +	fails = compare_bufs(&src, &final, true);
> +	if (!HAS_FLATCCS(devid)) {
> +		compressed = count_compressed(ibb->gen, &dst);
> +		igt_debug("fails: %u, compressed: %u\n", fails, compressed);
> +	} else {
> +		igt_debug("fails: %u\n", fails);
> +	}
>   
>   	if (write_png) {
> -		intel_buf_write_to_png(&src, "render-ccs-src.png");
> -		intel_buf_write_to_png(&dst, "render-ccs-dst.png");
> -		intel_buf_write_to_png(&dst2, "render-ccs-dst2.png");
> -		intel_buf_write_aux_to_png(&dst, "render-ccs-dst-aux.png");
> -		intel_buf_write_aux_to_png(&dst2, "render-ccs-dst2-aux.png");
> -		intel_buf_write_to_png(&final, "render-ccs-final.png");
> +		intel_buf_raw_write_to_png(&src, "render-ccs-src.png");
> +		intel_buf_raw_write_to_png(&dst, "render-ccs-dst.png");
> +		intel_buf_raw_write_to_png(&dst2, "render-ccs-dst2.png");
> +		intel_buf_raw_write_to_png(&final, "render-ccs-final.png");
> +		if (!HAS_FLATCCS(devid)) {
> +			intel_buf_write_aux_to_png(&dst, "render-ccs-dst-aux.png");
> +			intel_buf_write_aux_to_png(&dst2, "render-ccs-dst2-aux.png");
> +		}
>   	}
>   
>   	intel_buf_close(bops, &src);