[PATCH 3/3] lib/amdgpu: fix gfx11 issue about amd_dispatch
Jesse Zhang
jesse.zhang at amd.com
Thu Jun 20 06:15:41 UTC 2024
add some initialized register and fix some uncorrected register setting.
Signed-off-by: Jesse Zhang <Jesse.Zhang at amd.com>
Signed-off-by: Jiadong Zhu <Jiadong.Zhu at amd.com>
---
lib/amdgpu/amd_dispatch.c | 2 +-
lib/amdgpu/amd_dispatch_helpers.c | 34 ++++++++++++++++++++-----------
lib/amdgpu/amd_shaders.c | 3 +--
3 files changed, 24 insertions(+), 15 deletions(-)
diff --git a/lib/amdgpu/amd_dispatch.c b/lib/amdgpu/amd_dispatch.c
index b739ce64d..df7d56ea7 100644
--- a/lib/amdgpu/amd_dispatch.c
+++ b/lib/amdgpu/amd_dispatch.c
@@ -345,7 +345,7 @@ amdgpu_memcpy_dispatch_hang_slow_test(amdgpu_device_handle device_handle,
int r, r2;
int bo_dst_size = 0x4000000;
- int bo_shader_size = 0x400000;
+ int bo_shader_size = 0x4000000;
int bo_cmd_size = 4096;
struct amdgpu_cs_request ibs_request = {0};
diff --git a/lib/amdgpu/amd_dispatch_helpers.c b/lib/amdgpu/amd_dispatch_helpers.c
index 1c7413922..b0a5f550e 100644
--- a/lib/amdgpu/amd_dispatch_helpers.c
+++ b/lib/amdgpu/amd_dispatch_helpers.c
@@ -70,8 +70,20 @@
base->emit(base, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
base->emit(base, 0x7b);
base->emit(base, 0x20);
+ } else if (version == 11) {
+ base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG, 1));
+ base->emit(base, 0x222);
+ base->emit(base, 0);
+ base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG, 4));
+ base->emit(base, 0x224);
+ base->emit(base, 0);
+ base->emit(base, 0);
+ base->emit(base, 0);
+ base->emit(base, 0);
+ base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG, 1));
+ base->emit(base, 0x22a);
+ base->emit(base, 0);
}
-
return base->cdw - i;
}
@@ -85,27 +97,20 @@ int amdgpu_dispatch_write_cumask(struct amdgpu_cmd_base * base, uint32_t version
base->emit(base, 0x216);
base->emit(base, 0xffffffff);
base->emit(base, 0xffffffff);
- } else if(version == 10) {
+ } else if((version == 10) || (version == 11)) {
/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2));
base->emit(base, 0x30000216);
base->emit(base, 0xffffffff);
base->emit(base, 0xffffffff);
- /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
- base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2));
- base->emit(base, 0x30000219);
- base->emit(base, 0xffffffff);
- base->emit(base, 0xffffffff);
}
-
-
- /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
- base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG, 2));
+ /* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
+ base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG_INDEX, 2));
base->emit(base, 0x219);
base->emit(base, 0xffffffff);
base->emit(base, 0xffffffff);
- return base->cdw - offset_prev;
+ return base->cdw - offset_prev;
}
@@ -161,6 +166,11 @@ int amdgpu_dispatch_write2hw(struct amdgpu_cmd_base * base, uint64_t shader_addr
base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG, 1));
base->emit(base,0x228);
base->emit(base, 0 );
+ } else if (version == 11) {
+ /* mmCOMPUTE_PGM_RSRC3 */
+ base->emit(base, PACKET3_COMPUTE(PKT3_SET_SH_REG, 1));
+ base->emit(base,0x228);
+ base->emit(base, 0x3f0 );
}
return base->cdw - offset_prev;
}
diff --git a/lib/amdgpu/amd_shaders.c b/lib/amdgpu/amd_shaders.c
index fad6dbced..e4931961c 100644
--- a/lib/amdgpu/amd_shaders.c
+++ b/lib/amdgpu/amd_shaders.c
@@ -132,7 +132,6 @@ int amdgpu_dispatch_load_cs_shader_hang_slow(uint32_t *ptr, uint32_t family_id)
0xd7460000, 0x04010c08, 0xe00c2000, 0x80000100,
0xbf8c0f70, 0xe01ca000, 0x80010100, 0xbf810000
};
-
struct amdgpu_test_shader memcpy_cs_hang_slow_nv = {
memcpy_cs_hang_slow_nv_codes,
4,
@@ -140,7 +139,7 @@ int amdgpu_dispatch_load_cs_shader_hang_slow(uint32_t *ptr, uint32_t family_id)
1
};
struct amdgpu_test_shader *shader;
- int i, loop = 0x10000;
+ int i, loop = 0x100000;
switch (family_id) {
case AMDGPU_FAMILY_AI:
--
2.25.1
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