[PATCH i-g-t 3/4] lib/rendercopy_gen9: Add Tile64 support for render-copy

[Zbigniew Kempczyński]

Refactor a bit handling different tilings in render-copy pipeline
and add Tile64 which I want to exercise in xe_render_copy test.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski at intel.com>
Cc: Matthew Auld <matthew.auld at intel.com>
---
 lib/rendercopy_gen9.c | 24 +++++++++++++++++-------
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index efd7cb37c1..2b66e15ee6 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -191,19 +191,29 @@ gen9_bind_buf(struct intel_bb *ibb, const struct intel_buf *buf, int is_dst,
 		ss->ss5.mip_tail_start_lod = 1; /* needed with trmode */
 	}
 
-	if (buf->tiling == I915_TILING_X)
+	switch (buf->tiling) {
+	case I915_TILING_NONE:
+		ss->ss0.tiled_mode = 0;
+		break;
+	case I915_TILING_X:
 		ss->ss0.tiled_mode = 2;
-	else if (buf->tiling != I915_TILING_NONE)
+		break;
+	case I915_TILING_64:
+		ss->ss0.tiled_mode = 1;
+		ss->ss5.mip_tail_start_lod = 0xf;
+		break;
+	default:
 		ss->ss0.tiled_mode = 3;
+		if (buf->tiling == I915_TILING_Yf)
+			ss->ss5.trmode = 1;
+		else if (buf->tiling == I915_TILING_Ys)
+			ss->ss5.trmode = 2;
+		break;
+	}
 
 	if (intel_buf_pxp(buf))
 		ss->ss1.pxp = 1;
 
-	if (buf->tiling == I915_TILING_Yf)
-		ss->ss5.trmode = 1;
-	else if (buf->tiling == I915_TILING_Ys)
-		ss->ss5.trmode = 2;
-
 	address = intel_bb_offset_reloc(ibb, buf->handle,
 					read_domain, write_domain,
 					intel_bb_offset(ibb) + 4 * 8,
-- 
2.34.1