[PATCH i-g-t] lib/xe_spin: Fix MI_STORE_REGISTER_MEM instruction usage

[Matt Roper]

The MI_STORE_REGISTER_MEM macro in IGT's instruction header is the "old"
version of this define, intended for use on pre-gen8 platforms since it
bakes in the fixed 3-dword instruction length in the instruction header.
For gen8 and beyond (i.e., every platform the Xe driver supports), the
MI_STORE_REGISTER_MEM_GEN8 macro should be used instead, which properly
bakes in the 4-dword instruction length.  Since the xe_spin library was
using the old macro, but then manually |'ing in a "2" at the end of the
expression, it was effectively winding up with a field value of 3 (which
would represent a 5-dword instruction).

Switch xe_spin to using the "GEN8" macro and drop the redundant "| 2"
which is already handled by the macro itself.

Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
---
 lib/xe/xe_spin.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/xe/xe_spin.c b/lib/xe/xe_spin.c
index 2c531e85e..1ca54ea19 100644
--- a/lib/xe/xe_spin.c
+++ b/lib/xe/xe_spin.c
@@ -114,7 +114,7 @@ void xe_spin_init(struct xe_spin *spin, struct xe_spin_opts *opts)
 		spin->batch[b++] = MI_MATH_STOREINV(MI_MATH_REG(NOW_TS), MI_MATH_REG_ACCU);
 
 		/* Save delta for reading by COND_BBE */
-		spin->batch[b++] = MI_STORE_REGISTER_MEM | MI_SRM_CS_MMIO | 2;
+		spin->batch[b++] = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_CS_MMIO;
 		spin->batch[b++] = CS_GPR(NOW_TS);
 		spin->batch[b++] = ticks_delta_addr;
 		spin->batch[b++] = ticks_delta_addr >> 32;
-- 
2.43.0