[PATCH i-g-t 2/2] tests/intel/xe_exec_compute_mode: Test to validate LR mode
sai.gowtham.ch at intel.com
sai.gowtham.ch at intel.com
Fri Mar 15 05:04:38 UTC 2024
From: Sai Gowtham Ch <sai.gowtham.ch at intel.com>
Test to validate LR mode flag by submitting workload for
30's.
Signed-off-by: Sai Gowtham Ch <sai.gowtham.ch at intel.com>
---
tests/intel/xe_exec_compute_mode.c | 76 ++++++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/tests/intel/xe_exec_compute_mode.c b/tests/intel/xe_exec_compute_mode.c
index 7dad71509..7170bc746 100644
--- a/tests/intel/xe_exec_compute_mode.c
+++ b/tests/intel/xe_exec_compute_mode.c
@@ -400,6 +400,79 @@ static void non_block(int fd, int expect)
xe_vm_destroy(fd, vm);
}
+/**
+ * SUBTEST: lr-mode-workload
+ * Description: Stress LR mode workload for 30s.
+ * Test category: functionality test
+ */
+static void lr_mode_workload(int fd)
+{
+ uint64_t addr = 0x1a0000;
+ struct drm_xe_sync sync[1] = {
+ {.type = DRM_XE_SYNC_TYPE_USER_FENCE,
+ .flags = DRM_XE_SYNC_FLAG_SIGNAL,
+ .timeline_value = USER_FENCE_VALUE},
+ };
+ struct drm_xe_exec exec = {
+ .num_batch_buffer = 1,
+ .num_syncs = 1,
+ .syncs = to_user_pointer(&sync),
+ };
+ struct {
+ struct xe_spin spin;
+ uint64_t vm_sync;
+ uint32_t data;
+ uint64_t exec_sync;
+ } *data;
+ struct xe_spin_opts spin_opts;
+ struct drm_xe_engine *engine;
+ size_t bo_size;
+ uint32_t vm;
+ uint32_t exec_queue;
+ uint32_t bo;
+ uint32_t ts_1, ts_2;
+
+ vm = xe_vm_create(fd, DRM_XE_VM_CREATE_FLAG_LR_MODE, 0);
+ bo_size = sizeof(*data);
+ bo_size = xe_bb_size(fd, bo_size);
+
+ engine = xe_engine(fd, 1);
+ bo = xe_bo_create(fd, vm, bo_size, vram_if_possible(fd, engine->instance.gt_id), 0);
+
+ data = xe_bo_map(fd, bo, bo_size);
+ memset(data, 0, bo_size);
+ exec_queue = xe_exec_queue_create(fd, vm, &engine->instance, 0);
+ spin_opts.addr = addr + (char *)&data[SPIN_DATA].spin - (char *)data;
+
+ sync[0].addr = to_user_pointer(&data[0].vm_sync);
+ xe_vm_bind_async(fd, vm, engine->instance.gt_id, bo, 0, addr, bo_size, sync, 1);
+ xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC);
+ data[0].vm_sync = 0;
+
+ spin_opts.write_timestamp = true;
+ xe_spin_init(&data[SPIN_DATA].spin, &spin_opts);
+ sync[0].addr = addr + (char *)&data[SPIN_DATA].exec_sync - (char *)data;
+ exec.exec_queue_id = exec_queue;
+ exec.address = spin_opts.addr;
+ xe_exec(fd, &exec);
+ xe_spin_wait_started(&data[SPIN_DATA].spin);
+ sleep(30);
+ ts_1 = data[SPIN_DATA].spin.time_stamp;
+ sleep(10);
+ ts_2 = data[SPIN_DATA].spin.time_stamp;
+ xe_spin_end(&data[SPIN_DATA].spin);
+ igt_assert(ts_1 != ts_2);
+
+ sync[0].addr = to_user_pointer(&data[0].vm_sync);
+ xe_vm_unbind_async(fd, vm, 0, 0, addr, bo_size, sync, 1);
+ xe_wait_ufence(fd, &data[0].vm_sync, USER_FENCE_VALUE, 0, ONE_SEC);
+ munmap(data, bo_size);
+ gem_close(fd, bo);
+
+ xe_exec_queue_destroy(fd, exec_queue);
+ xe_vm_destroy(fd, vm);
+}
+
igt_main
{
struct drm_xe_engine_class_instance *hwe;
@@ -460,6 +533,9 @@ igt_main
igt_subtest("non-blocking")
non_block(fd, EWOULDBLOCK);
+ igt_subtest("lr-mode-workload")
+ lr_mode_workload(fd);
+
igt_fixture
drm_close_driver(fd);
--
2.39.1
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